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ATWILC1000B-MUT データシート(PDF) 15 Page - ATMEL Corporation

部品番号 ATWILC1000B-MUT
部品情報  IEEE 802.11 b/g/n Link Controller SoC
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メーカー  ATMEL [ATMEL Corporation]
ホームページ  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

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ATWILC1000B-MUT [DATASHEET]
Atmel-42491B-ATWILC1000B-MUT_Datasheet_03/2016
1
5
15
6
CPU and Memory Subsystems
6.1
Processor
ATWILC1000B has a Cortus APS3 32-bit processor. This processor performs many of the MAC functions,
including but not limited to association, authentication, power management, security key management, and
MSDU aggregation/de-aggregation. In addition, the processor provides flexibility for various modes of
operation, such as STA and AP modes.
6.2
Memory Subsystem
The APS3 core uses a 128KB instruction/boot ROM along with a 160KB instruction RAM and a 64KB data
RAM. In addition, the device uses a 128KB shared RAM, accessible by the processor and MAC, which allows
the APS3 core to perform various data management tasks on the TX and RX data packets.
6.3
Non-volatile Memory (eFuse)
ATWILC1000B has 768 bits of non-volatile eFuse memory that can be read by the CPU after device reset. This
non-volatile one-time-programmable (OTP) memory can be used to store customer-specific parameters, such
as MAC address; various calibration information, such as TX power, crystal frequency offset, etc.; and other
software-specific configuration parameters. The eFuse is partitioned into six 128-bit banks. Each bank has the
same bit map, which is shown in Figure 6-1. The purpose of the first 80 bits in each bank is fixed, and the
remaining 48 bits are general-purpose software dependent bits, or reserved for future use. Since each bank
can be programmed independently, this allows for several updates of the device parameters following the initial
programming e.g., updating MAC address. Refer to ATWILC1000B Programming Guide for the eFuse
programming instructions.
Figure 6-1.
eFuse Bit Map
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
F
MAC ADDR
FO
Flags
G
3
1
1
4
1
1
7
48
8
8
16
1
15
128 Bits


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