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SLG46127 データシート(PDF) 72 Page - Dialog Semiconductor

部品番号 SLG46127
部品情報  GreenPAK Programmable Mixed-signal Matrix
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SLG46127 データシート(HTML) 72 Page - Dialog Semiconductor

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Page 71 of 87
SLG46127
19.0 Appendix A - SLG46127 Register Definition
Register Bit
Address
Signal Function
Register Bit Definition
reg <4:0>
Matrix Out: PIN14 Digital Output Source
reg <9:5>
Matrix Out: PIN1 Digital Output Source
reg <14:10>
Matrix Out: PIN2 Digital Output Source
reg <19:15>
Matrix Out: Output Enable of PIN2
reg <24:20>
Matrix Out: In0 of LUT2_0 or Clock Input of DFF0
reg <29:25>
Matrix Out: In1 of LUT2_0 or Data Input of DFF0
reg <34:30>
Matrix Out: In0 of LUT2_1 or Clock Input of DFF1
reg <39:35>
Matrix Out: In1 of LUT2_1 or Data Input of DFF1
reg <44:40>
Matrix Out: In0 of LUT2_2
reg <49:45>
Matrix Out: In1 of LUT2_2
reg <54:50>
Matrix Out: In0 of LUT2_3
reg <59:55>
Matrix Out: In1 of LUT2_3
reg <64:60>
Matrix Out: In0 of LUT3_0 or Clock Input of DFF2
reg <69:65>
Matrix Out: In1 of LUT3_0 or Data Input of DFF2
reg <74:70>
Matrix Out: In2 of LUT3_0 or nRST Input of DFF2
reg <79:75>
Matrix Out: In0 of LUT3_1 or Clock Input of DFF3
reg <84:80>
Matrix Out: In1 of LUT3_1 or Data Input of DFF3
reg <89:85>
Matrix Out: In2 of LUT3_1 or nRST (nSET) of DFF3
reg <94:90>
Matrix Out: In0 of LUT3_2
reg <99:95>
Matrix Out: In1 of LUT3_2
reg <104:100>
Matrix Out: In2 of LUT3_2
reg <109:105>
Matrix Out: In0 of LUT3_3
reg <114:110>
Matrix Out: In1 of LUT3_3
reg <119:115>
Matrix Out: In2 of LUT3_3
reg <124:120>
Matrix Out: In0 of LUT3_4 or Input of Pipe Delay
reg <129:125>
Matrix Out: In1 of LUT3_4 or nRST of Pipe Delay
reg <134:130>
Matrix Out: In2 of LUT3_4 or Clock of Pipe Delay
reg <139:135>
Matrix Out: In0 of LUT4_0 or Input for Delay2 (Counter2)
external clock
reg <144:140>
Matrix Out: In1 of LUT4_0 or Input for Delay2 data
(Counter2 reset)
reg <149:145>
Matrix Out: In2 of LUT4_0
reg <154:150>
Matrix Out: In3 of LUT4_0
reg <159:155> Matrix Out: Input for Delay0 data (Counter0 reset)
reg <164:160>
Matrix Out: Input for Delay1 data (Counter1 reset)
reg <169:165>
Matrix Out: Input for Delay0/1 (Counter0/1) external
clock
reg <174:170>
Matrix Out: Input for Delay3 (Counter3) external clock
reg <179:175> Matrix Out: pdb (power down) for ACMP0
reg <184:180> Matrix Out: pdb (power down) for ACMP1
reg <189:185>
Matrix Out: Input for programmable Delay (deglitch filter
input)


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