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SLG46200 データシート(PDF) 32 Page - Dialog Semiconductor |
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SLG46200 データシート(HTML) 32 Page - Dialog Semiconductor |
32 / 69 page 000-0046200-124 Page 27 of 64 SLG46200 12.0 Analog Comparator (ACMP) There are two Analog Comparator (ACMP) macro cells in the SLG46200. In order for the ACMP cells to be used in a GreenPAK design the power up signals (PWR UP) need to be active. Each of the two ACMP cells have positive and negative input signals that are either created from an internal VREF or provided by way of the external sources. The two analog comparators (ACMP0 and ACMP1) must have the same power state (on or off). The Power Up input is set to high to turn on the analog comparators, and the comparators are turned off when the Power Up input is low. When the analog comparators are turned off, they both have an output that is logic high. Also note that the ACMP output is unpredictable for 100 μs after power on (except after POR). 12.1 ACMP0 Input Modes ACMP0’s positive input (IN+) can be enabled from PIN 4 or ADC/PGA out by the ACMP0_PGA_en signal, reg<357>. The negative input (IN-) of the ACMP0 cell can come from the internal VREF macro cell (which will generate a 50mV to 1.5V signal) or from an external voltage source that is placed on PIN 8. Selection is made using a 4-bit value from NVM, reg<361:358>. 12.2 ACMP0 Functional Diagram 12.3 ACMP1 Input Modes ACMP1’s positive input (IN+) comes from PIN 7 with selection gain of 1X or 0.5X (two 50k Ω resistor divider). The ACMP1_0.5gain_en signal (reg<345>) is used as a control signal into a mux which has the 1X and 0.5X signals as inputs. The negative input (IN-) of the ACMP1 cell can come from the internal VREF macro cell (which will generate a 50mV to 1.5V signal) or from an external voltage source that is placed on PIN 8. Selection is made using a 4-bit value from NVM, reg<366:363>. Figure 15. ACMP0 Functional Diagram 0.05V 1.5V ACMP0 reg <361:358> 1 0 PIN 4 reg <369> reg <357> IN- IN+ PWR UP … … … 0.1V PIN 8 0000 1111 0001 1110 … … … 1.3V 1101 reg <347> To Connection Matrix input <17> From Connection Matrix output <5> reg <346> From ADC PGA OUT |
同様の部品番号 - SLG46200 |
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同様の説明 - SLG46200 |
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