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CY2XP311 データシート(PDF) 9 Page - Cypress Semiconductor

部品番号 CY2XP311
部品情報  312.5 MHz LVPECL Clock Generator
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メーカー  CYPRESS [Cypress Semiconductor]
ホームページ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY2XP311 データシート(HTML) 9 Page - Cypress Semiconductor

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CY2XP311
Document Number: 001-59931 Rev. *E
Page 9 of 14
Application Information
Power Supply Filtering Techniques
As in any high speed analog circuitry, noise at the power supply
pins can degrade performance. To achieve optimum jitter
performance, use good power supply isolation practices.
Figure 9 illustrates a typical filtering scheme. 0.01 to 0.1 µF
ceramic chip capacitors are located close to the VDD pins to
provide a short and low impedance AC path to ground. A 1 to 10
µF ceramic or tantalum capacitor is located in the general vicinity
of this device and may be shared with other devices. An
acceptable alternative power supply configuration is shown in
Figure 10.
Figure 9. Power Supply Filtering
Figure 10. Alternative Power Supply Filtering
Termination for LVPECL Output
The CY2XP311 implements its LVPECL driver with a current
steering design. For proper operation, it requires a 50 ohm dc
termination on each of the two output signals. For 3.3 V
operation, this data sheet specifies output levels for termination
to VDD–2.0 V. This same termination voltage can also be used
for VDD = 2.5 V operation, or it can be terminated to VDD–1.5 V.
Note that it is also possible to terminate with 50 ohms to ground
(VSS), but the high and low signal levels differ from the data sheet
values. Termination resistors are best located close to the
destination device. To avoid reflections, trace characteristic
impedance (Z0) should match the termination impedance.
Figure 11 shows a standard termination scheme.
Figure 11. LVPECL Output Termination
Crystal Input Interface
The CY2XP311 is characterized with 18 pF parallel resonant
crystals. The capacitor values shown in Figure 12 are
determined using a 25 MHz 18 pF parallel resonant crystal and
are chosen to minimize the ppm error. Note that the optimal
values for C1 and C2 depend on the parasitic trace capacitance
and are therefore layout dependent.
Figure 12. Crystal Input Interface
3.3V or 2.5V
0.01µF
VDD
(Pin 1)
VDD
(Pin 8)
0.01µF
10µF
3.3V or 2.5V
0.01µF
VDD
(Pin 1)
VDD
(Pin 8)
0.01µF
10µF
10
CLK
84
84
Z0 = 50
Z0 = 50
3.3V
125
125
IN
CLK#
Device
XIN
XOUT
X1
18 pF Parallel
Crystal
C1
33 pF
C2
27 pF


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