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CY7C1460KV25 データシート(PDF) 22 Page - Cypress Semiconductor

部品番号 CY7C1460KV25
部品情報  36-Mbit (1M36/2M18) Pipelined SRAM with NoBL??Architecture (With ECC)
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メーカー  CYPRESS [Cypress Semiconductor]
ホームページ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1460KV25 データシート(HTML) 22 Page - Cypress Semiconductor

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Document Number: 001-66679 Rev. *J
Page 22 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
IDD
VDD operating supply
VDD = Max,
IOUT = 0 mA,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
× 18
220
mA
× 36
240
5-ns cycle,
200 MHz
× 18
190
mA
× 36
210
6-ns cycle,
167 MHz
× 18
170
mA
× 36
190
ISB1
Automatic CE power-down
current – TTL inputs
Max VDD,
device deselected,
VIN  VIH or VIN  VIL,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
× 18
85
mA
× 36
90
5-ns cycle,
200 MHz
× 18
85
mA
× 36
90
6-ns cycle,
167 MHz
× 18
85
mA
× 36
90
ISB2
Automatic CE power-down
current – CMOS inputs
Max VDD,
device deselected,
VIN  0.3 V or
VIN > VDDQ 0.3 V,
f = 0
All speeds
× 18
75
mA
× 36
80
ISB3
Automatic CE power-down
current – CMOS inputs
Max VDD,
device deselected,
VIN  0.3 V or
VIN > VDDQ 0.3 V,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
× 18
85
mA
× 36
90
5-ns cycle,
200 MHz
× 18
85
mA
× 36
90
6-ns cycle,
167 MHz
× 18
85
mA
× 36
90
ISB4
Automatic CE power-down
current – TTL inputs
Max VDD,
device deselected,
VIN  VIH or VIN  VIL,
f = 0
All speed
grades
× 18
75
mA
× 36
80
mA
Electrical Characteristics (continued)
Over the Operating Range
Parameter [16, 17]
Description
Test Conditions
Min
Max
Unit


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