CY7C1461KV33

CY7C1463KV33

Document Number: 001-66681 Rev. *G

Page 15 of 23

Switching Characteristics

Over the Operating Range

Parameter [13, 14]

Description

133 MHz

Unit

Min

Max

–

1

–

ms

Clock

Clock Cycle Time

7.5

–

ns

Clock HIGH

2.5

–

ns

Clock LOW

2.5

–

ns

Output Times

Data Output Valid After CLK Rise

–

6.5

ns

Data Output Hold After CLK Rise

2.5

–

ns

Clock to Low Z [16, 17, 18]

2.5

–

ns

Clock to High Z [16, 17, 18]

–

3.8

ns

OE LOW to Output Valid

–

3.0

ns

OE LOW to Output Low Z [16, 17, 18]

0

–

ns

OE HIGH to Output High Z [16, 17, 18]

–

3.0

ns

Setup Times

Address Setup Before CLK Rise

1.5

–

ns

ADV/LD Setup Before CLK Rise

1.5

–

ns

1.5

–

ns

CEN Setup Before CLK Rise

1.5

–

ns

Data Input Setup Before CLK Rise

1.5

–

ns

Chip Enable Setup Before CLK Rise

1.5

–

ns

Hold Times

Address Hold After CLK Rise

0.5

–

ns

ADV/LD Hold After CLK Rise

0.5

–

ns

0.5

–

ns

CEN Hold After CLK Rise

0.5

–

ns

Data Input Hold After CLK Rise

0.5

–

ns

Chip Enable Hold After CLK Rise

0.5

–

ns

Notes

14. Test conditions shown in (a) of Figure 3 on page 14 unless otherwise noted.

can be initiated.

These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve

High Z prior to Low Z under the same system conditions.

18. This parameter is sampled and not 100% tested.