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CY7C1521KV18 データシート(PDF) 23 Page - Cypress Semiconductor

部品番号 CY7C1521KV18
部品情報  72-Mbit DDR II SRAM Four-Word Burst Architecture
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メーカー  CYPRESS [Cypress Semiconductor]
ホームページ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1521KV18 データシート(HTML) 23 Page - Cypress Semiconductor

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Document Number: 001-00439 Rev. *M
Page 23 of 29
CY7C1521KV18
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K in single clock mode) to Data Valid
0.45
ns
tDOH
tCHQX
Data Output Hold after Output C/C Clock Rise (Active to Active)
–0.45
ns
tCCQO
tCHCQV
C/C Clock Rise to Echo Clock Valid
0.45
ns
tCQOH
tCHCQX
Echo Clock Hold after C/C Clock Rise
–0.45
ns
tCQD
tCQHQV
Echo Clock High to Data Valid
0.30
ns
tCQDOH
tCQHQX
Echo Clock High to Data Invalid
–0.30
ns
tCQH
tCQHCQL
Output Clock (CQ/CQ) HIGH [28]
1.75
ns
tCQHCQH
tCQHCQH
CQ Clock Rise to CQ Clock Rise (rising edge to rising edge) [28]
1.75
ns
tCHZ
tCHQZ
Clock (C/C) Rise to High-Z (Active to High-Z) [29, 30]
0.45
ns
tCLZ
tCHQX1
Clock (C/C) Rise to Low-Z [29, 30]
–0.45
ns
PLL Timing
tKC Var
tKC Var
Clock Phase Jitter
0.20
ns
tKC lock
tKC lock
PLL Lock Time (K, C)
20
s
tKC Reset
tKC Reset
K Static to PLL Reset
30
ns
Switching Characteristics (continued)
Over the Operating Range
Parameters [25, 26]
Description
250 MHz
Unit
Cypress
Parameter
Consortium
Parameter
Min
Max
Notes
28. These parameters are extrapolated from the input timing parameters (tCYC/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
design and are not tested in production.
29. tCHZ, tCLZ are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 21. Transition is measured 100 mV from steady-state voltage.
30. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.


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