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CY7C1563XV18 データシート(PDF) 20 Page - Cypress Semiconductor

部品番号 CY7C1563XV18
部品情報  72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
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メーカー  CYPRESS [Cypress Semiconductor]
ホームページ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1563XV18 データシート(HTML) 20 Page - Cypress Semiconductor

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Document Number: 001-70205 Rev. *G
Page 20 of 29
CY7C1563XV18/CY7C1565XV18
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Supply Voltage on VDD Relative to GND .....–0.5 V to +2.9 V
Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD
DC Applied to Outputs in High Z ....... –0.5 V to VDDQ + 0.3 V
DC Input Voltage [20] ........................... –0.5 V to VDD + 0.3 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, M. 3015) ....................................... > 2,001 V
Latch up Current ................................................... > 200 mA
Maximum Junction temperature..................................125 °C
Operating Range
Range
Ambient
Temperature (TA)
VDD [21]
VDDQ [21]
Commercial
0 °C to +70 °C
1.8 ± 0.1 V 1.4 V to 1.6 V
Neutron Soft Error Immunity
Parameter Description
Test
Conditions Typ Max* Unit
LSBU
Logical
Single-Bit
Upsets
25 °C
260
271
FIT/
Mb
LMBU
Logical
Multi-Bit
Upsets
25 °C
0
0.01
FIT/
Mb
SEL
Single Event
Latch up
85 °C
0
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
statistical
2, 95% confidence limit calculation. For more details refer to
Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of
Terrestrial Failure Rates”.
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Over the Operating Range
Parameter [22]
Description
Test Conditions
Min
Typ
Max
Unit
VDD
Power Supply Voltage
1.7
1.8
1.9
V
VDDQ
I/O Supply Voltage
1.4
1.5
1.6
V
VOH
Output HIGH Voltage
Note 23
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOL
Output LOW Voltage
Note 24
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOH(LOW)
Output HIGH Voltage
IOH =0.1 mA, Nominal Impedance
VDDQ – 0.2
VDDQ
V
VOL(LOW)
Output LOW Voltage
IOL = 0.1 mA, Nominal Impedance
VSS
–0.2
V
VIH
Input HIGH Voltage
VREF + 0.1
VDDQ + 0.15
V
VIL
Input LOW Voltage
–0.15
VREF – 0.1
V
IX
Input Leakage Current
GND
 VI  VDDQ
2–
2
A
IOZ
Output Leakage Current
GND
 VI  VDDQ, Output Disabled
2–
2
A
VREF
Input Reference Voltage
Typical Value = 0.75 V
0.68
0.75
0.86
V
Notes
20. Overshoot: VIH(AC) < VDDQ + 0.35 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2).
21. Power up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
22. All Voltage referenced to Ground.
23. Outputs are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175 ohms < RQ < 350 ohms.
24. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 ohms < RQ < 350 ohms.


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