CY7C1648KV18 datasheet(3/29 Pages) CYPRESS

部品番号	CY7C1648KV18

部品情報	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)

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メーカー	CYPRESS [Cypress Semiconductor]

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Document Number: 001-44061 Rev. *L

Page 3 of 29

CY7C1648KV18

CY7C1650KV18

Contents

Pin Configurations ........................................................... 4

Pin Definitions .................................................................. 5

Functional Overview ........................................................ 6

Read Operations ......................................................... 6

Write Operations ......................................................... 6

Byte Write Operations ................................................. 6

DDR Operation ............................................................ 6

Depth Expansion ......................................................... 6

Programmable Impedance .......................................... 7

Echo Clocks ................................................................ 7

Valid Data Indicator (QVLD) ........................................ 7

PLL .............................................................................. 7

Application Example ........................................................ 7

Truth Table ........................................................................ 8

Write Cycle Descriptions ................................................. 8

Write Cycle Descriptions ................................................. 9

IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 10

Disabling the JTAG Feature ...................................... 10

Test Access Port ....................................................... 10

Performing a TAP Reset ........................................... 10

TAP Registers ........................................................... 10

TAP Instruction Set ................................................... 10

TAP Controller State Diagram ....................................... 12

TAP Controller Block Diagram ...................................... 13

TAP Electrical Characteristics ...................................... 13

TAP AC Switching Characteristics ............................... 14

TAP Timing and Test Conditions .................................. 15

Identification Register Definitions ................................ 16

Scan Register Sizes ....................................................... 16

Instruction Codes ........................................................... 16

Boundary Scan Order .................................................... 17

Power Up Sequence in DDR II+ SRAM ......................... 18

Power Up Sequence ................................................. 18

PLL Constraints ......................................................... 18

Maximum Ratings ........................................................... 19

Operating Range ............................................................. 19

Neutron Soft Error Immunity ......................................... 19

Electrical Characteristics ............................................... 19

DC Electrical Characteristics ..................................... 19

AC Electrical Characteristics ..................................... 21

Capacitance .................................................................... 21

Thermal Resistance ........................................................ 21

AC Test Loads and Waveforms ..................................... 21

Switching Characteristics .............................................. 22

Switching Waveforms .................................................... 23

Read/Write/Deselect Sequence ................................ 23

Ordering Information ...................................................... 24

Ordering Code Definitions ......................................... 24

Package Diagram ............................................................ 25

Acronyms ........................................................................ 26

Document Conventions ................................................. 26

Units of Measure ....................................................... 26

Document History Page ................................................. 27

Sales, Solutions, and Legal Information ...................... 29

Worldwide Sales and Design Support ....................... 29

Products .................................................................... 29

PSoC® Solutions ...................................................... 29

Cypress Developer Community ................................. 29

Technical Support ..................................................... 29

同様の部品番号 - CY7C1648KV18

メーカー	部品番号	データシート	部品情報
Cypress Semiconductor	CY7C1648KV18-400BZXC	857Kb / 30P	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
Cypress Semiconductor	CY7C1648KV18	857Kb / 30P	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)

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同様の説明 - CY7C1648KV18

メーカー	部品番号	データシート	部品情報
Cypress Semiconductor	CY7C1648KV18	857Kb / 30P	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
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