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S29GL01GP データシート(PDF) 43 Page - Cypress Semiconductor

部品番号 S29GL01GP
部品情報  1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash with 90 nm MirrorBit Process Technology
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メーカー  CYPRESS [Cypress Semiconductor]
ホームページ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

S29GL01GP データシート(HTML) 43 Page - Cypress Semiconductor

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Document Number: 002-00886 Rev. *B
Page 43 of 83
S29GL01GP
S29GL512P
S29GL256P
S29GL128P
8.5
Advanced Sector Protection Software Examples
Table contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the status of the sector. In summary, if the
PPB Lock Bit is locked (set to “0”), no changes to the PPBs are allowed. The PPB Lock Bit can only be unlocked (reset to “1”)
through a hardware reset or power cycle. See also Figure 8.1 for an overview of the Advanced Sector Protection feature.
8.6
Hardware Data Protection Methods
The device offers two main types of data protection at the sector level via hardware control:
When WP#/ACC is at VIL, the either the highest or lowest sector is locked (device specific).
There are additional methods by which intended or accidental erasure of any sectors can be prevented via hardware means. The
following subsections describes these methods:
8.6.1
WP#/ACC Method
The Write Protect feature provides a hardware method of protecting one outermost sector. This function is provided by the WP#/
ACC pin and overrides the previously discussed Sector Protection/Unprotection method.
If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the highest or lowest sector
independently of whether the sector was protected or unprotected using the method described in Advanced Sector Protection/
Unprotection
on page 38.
If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the boot sectors were last set to be protected or
unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or
unprotected.
The WP#/ACC pin must be held stable during a command sequence execution. WP# has an internal pull-up; when unconnected,
WP# is set at VIH.
Note
If WP#/ACC is at VIL when the device is in the standby mode, the maximum input load current is increased. See Table 11.2
on page 50 for details.
8.6.2
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent
writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent
unintentional writes when VCC is greater than VLKO.
Sector Protection Schemes: DYB, PPB and PPB Lock Bit Combinations
Unique Device PPB Lock Bit
0 = locked
1 = unlocked
Sector PPB
0 = protected
1 = unprotected
Sector DYB
0 = protected
1 = unprotected
Sector Protection Status
Any Sector
0
0
x
Protected through PPB
Any Sector
0
0
x
Protected through PPB
Any Sector
0
1
1
Unprotected
Any Sector
0
1
0
Protected through DYB
Any Sector
1
0
x
Protected through PPB
Any Sector
1
0
x
Protected through PPB
Any Sector
1
1
0
Protected through DYB
Any Sector
1
1
1
Unprotected


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