AD6624A datasheet(5/40 Pages) AD

部品番号	AD6624A

部品情報	Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP)

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REV. 0

AD6624A

–5–

MICROPROCESSOR PORT TIMING CHARACTERISTICS1, 2

Test

AD6624AS

Parameter (Conditions)

Temp

Level

Min

Typ

Max

Unit

MICROPROCESSOR PORT, MODE INM (MODE = 0)

MODE INM Write Timing:

tSC

Control

3 to

↑CLK Setup Time

Full

IV

5.5

ns

tHC

Control

3 to

↑CLK Hold Time

Full

IV

1.0

ns

tHWR

WR(RW) to RDY(DTACK) Hold Time

Full

IV

8.0

ns

tSAM

Address/Data to

WR(RW) Setup Time

Full

IV

–0.5

ns

tHAM

Address/Data to RDY(

DTACK) Hold Time

Full

IV

7.0

ns

tDRDY

WR(RW) to RDY(DTACK) Delay

Full

IV

4.0

ns

tACC

WR(RW) to RDY(DTACK) High Delay

Full

IV

4

× tCLK 5 × tCLK 9 × tCLK

ns

MODE INM Read Timing:

tSC

Control3 to

↑CLK Setup Time

Full

IV

4.0

ns

tHC

Control

3 to

↑CLK Hold Time

Full

IV

2.0

ns

tSAM

Address to

RD(DS) Setup Time

Full

IV

0.0

ns

tHAM

Address to Data Hold Time

Full

IV

7.0

ns

tDRDY

RD(DS) to RDY(DTACK) Delay

Full

IV

4.0

ns

tACC

RD(DS) to RDY(DTACK) High Delay

Full

IV

8

× tCLK 10 × tCLK 13 × tCLK

ns

MICROPROCESSOR PORT, MODE MNM (MODE = 1)

MODE MNM Write Timing:

tSC

Control

3 to

↑CLK Setup Time

Full

IV

5.5

ns

tHC

Control

3 to

↑CLK Hold Time

Full

IV

1.0

ns

tHDS

DS(RD) to DTACK(RDY) Hold Time

Full

IV

8.0

ns

tHRW

RW(

WR) to DTACK(RDY) Hold Time

Full

IV

8.0

ns

tSAM

Address/Data to RW(

WR) Setup Time

Full

IV

–0.5

ns

tHAM

Address/Data to RW(

WR) Hold Time

Full

IV

7.0

ns

tACC

RW(

WR) to DTACK(RDY) Low Delay

Full

IV

4

× tCLK 5 × tCLK 9 × tCLK

ns

MODE MNM Read Timing:

tSC

Control

3 to

↑CLK Setup Time

Full

IV

4.0

ns

tHC

Control3 to

↑CLK Hold Time

Full

IV

2.0

ns

tSAM

Address to

DS(RD) Setup Time

Full

IV

0.0

ns

tHAM

Address to Data Hold Time

Full

IV

7.0

ns

tZD

Data Three-State Delay

Full

IV

7.0

ns

tACC

DS(RD) to DTACK(RDY) Low Delay

Full

IV

8

× tCLK 10 × tCLK 13 × tCLK

ns

NOTES

1All Timing Specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V.

2C

LOAD = 40 pF on all outputs unless otherwise specified.

3Specification pertains to control signals: RW, (

WR), DS, (RD), CS.

Specifications subject to change without notice.

同様の部品番号 - AD6624A

メーカー	部品番号	データシート	部品情報
Analog Devices	AD6624AS	509Kb / 40P	Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) REV. B
Analog Devices	AD6624A	642Kb / 40P	Four-Channel, 100 MSPS Digital Receive Signal Processor REV. 0

More results

同様の説明 - AD6624A

メーカー	部品番号	データシート	部品情報
Analog Devices	AD6624	509Kb / 40P	Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) REV. B
	AD6624A	642Kb / 40P	Four-Channel, 100 MSPS Digital Receive Signal Processor REV. 0
	AD6624	566Kb / 40P	Four-Channel, 80 MSPS Digital Receive Signal Processor REV. B
	AD6635	799Kb / 60P	4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) REV. 0
	AD6634	925Kb / 52P	80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) REV. 0
	AD6620ASZ	374Kb / 44P	67 MSPS Digital Receive Signal Processor REV. A
	AD6620	354Kb / 43P	65 MSPS Digital Receive Signal Processor REV. 0
	AD6620	399Kb / 44P	67 MSPS Digital Receive Signal Processor REV. A
	AD6620AS	399Kb / 44P	67 MSPS Digital Receive Signal Processor REV. A
	AD6622	242Kb / 28P	Four-Channel, 75 MSPS Digital Transmit Signal Processor REV. 0

More results

AD6624A データシート(PDF) 5 Page - Analog Devices

AD6624A データシート(HTML) 5 Page - Analog Devices

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