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FM1808-120-P データシート(PDF) 6 Page - List of Unclassifed Manufacturers |
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FM1808-120-P データシート(HTML) 6 Page - List of Unclassifed Manufacturers |
6 / 12 page Ramtron FM1808-70 27 July 2000 6/12 FRAM Design Considerations When designing with FRAM for the first time, users of SRAM will recognize a few minor differences. First, bytewide FRAM memories latch each address on the falling edge of chip enable. This allows the address bus to change after starting the memory access. Since every access latches the memory address on the falling edge of /CE, users should not ground it as they might with SRAM. Users that are modifying existing designs to use FRAM should examine the hardware address decoders. Decoders should be modified to qualify addresses with an address valid signal if they do not already. In many cases, this is the only change required. Systems that drive chip enable active, then inactive for each valid address may need no modifications. An example of the target signal relationships are shown in Figure 4. Also shown is a common SRAM signal relationship that will not work for the FM1808. The main design issue is to create a decoder scheme that will drive /CE active, then inactive for each address. This accomplishes the two goals of latching the new address and cre ating the precharge period. A second design consideration relates to the level of VDD during operation. Battery-backed SRAMs are forced to monitor VDD in order to switch to battery backup. They typically block user access below a certain VDD level in order to prevent loading the battery with current demand from an active SRAM. The user can be abruptly cut off from access to the nonvolatile memory in a power down situation with no warning or indication. FRAM memories do not need this system overhead. The memory will not block access at any VDD level. The user, however, should prevent the processor from accessing memory when VDD is out-of- tolerance. The common design practice of holding a processor in reset when VDD drops is adequate; no special provisions must be taken for FRAM design. Figure 4. Memory Address Relationships Valid Memory Read Relationship FRAM Signaling CE Address A1 A2 Data D1 D2 Invalid Memory Read Relationship SRAM Signaling CE Address A1 A2 Data D1 D2 |
同様の部品番号 - FM1808-120-P |
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同様の説明 - FM1808-120-P |
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