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AK4376A データシート(PDF) 36 Page - Asahi Kasei Microsystems |
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AK4376A データシート(HTML) 36 Page - Asahi Kasei Microsystems |
36 / 68 page [AK4376A] 016014206-E-00 2016/11 - 36 - ■ DACMCLK Generating Divider Setting MDIV[7:0] bits control DACMCLK divider. Table 13. DACMCLK Divider Setting MDIV[7:0] bits Dividing Number 00H 1 (default) 01H to FFH 1 / (MDIV + 1) ■ Crystal Oscillator The clock for the XTI pin can be generated by two methods. PMOSC bit must be set to “1” when using a crystal oscillator. 1) X ’tal Mode (PMOSC bit = “1”) XTI XTO AK4376A Figure 12. X ’tal Mode Note 69. The capacitor value is dependent on the crystal oscillator. CL = 21.5 pF (Max.), Rl (Equivalent Series Resistance) = 80Ω (Max.) @ 24.576 MHz CL = 30.6 pF (Max.), Rl (Equivalent Series Resistance) = 200Ω (Max.) @ 11.2896 MHz 2) External Clock Mode (PMOSC bit = “0”) XTI XTO AK4376A External Clock Figure 13. External Clock Mode Note 70. Do not input a clock more than AVDD. 3) OFF Mode (Not Using XTI/XTO pins (PMOSC bit = “0”)) XTI XTO AK4376A Figure 14. OFF Mode |
同様の部品番号 - AK4376A |
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同様の説明 - AK4376A |
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