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AK5522 データシート(PDF) 69 Page - Asahi Kasei Microsystems |
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AK5522 データシート(HTML) 69 Page - Asahi Kasei Microsystems |
69 / 84 page [AK5522] 017002311-E-00 2017/03 - 69 - External Slave Mode (Serial Control Mode) Figure 69. Power-up Sequence (Serial Control mode, EXT Slave Mode) (1) Input MCLK, LRCK and BICK after power on the power supplies. (2) Raise the PDN pin from “L” to “H”. The PDN pin should be held to “L” for more than 150 ns after power on the power supplies. (3) The Internal regulator for digital core powers up after 17.8ms (max.) from a rising edge of the PDN pin. This timing is counted by the internal oscillator. Register accesses will be valid after REGDO voltage is raised up. (4) The VREF pin outputs reference voltage after 35.7ms (max.@fs=48kHz) from the rising edge of the PDN pin. (5) The REGAO pin outputs 3.3V after 42.7ms (max.@fs=48kHz) from the rising edge of the PDN pin. (6) Set “1” into PDALN/PDARN bits after setting other registers. (7) The SDTO pin starts outputting A/D data after 64.6ms (max.@fs=48kHz) from PDALN/PDARN bit = “1”. Wait time (4), (5) and (6) depend on the sampling frequency as shown in the expressions below. (4): 27.8ms+378 n/fs (max.) (5): 22.8ms+953 n/fs (max.) (7): 3100 n/fs (max.) Normal speed: n=1, Double speed: n=2, Quad speed: n=4 AVDD pin DVDD pin MCLK pin (I) LRCK pin (I) BICK pin (I) PDN pin (I) (2) (1) REGDO pin (O) (DVDD=3.3V) (3) Hi-Z VREF pin (O) (4) Hi-Z (Pull-down) Output REGAO pin (O) (AVDD=5V) (5) Output SDTO pin (O) (7) Output REGDO pin (I) (DVDD=1.8V) REGAO pin (O) (AVDD=3.3V) Hi-Z (Pull-down) Hi-Z (Pull-down) PDADLN bit PDADRN bit (6) Register access is valid Register access is valid ADC Power down ADC Power up |
同様の部品番号 - AK5522 |
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同様の説明 - AK5522 |
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