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N02L163WN1AT2-55I データシート(PDF) 3 Page - NanoAmp Solutions, Inc.

部品番号 N02L163WN1AT2-55I
部品情報  2Mb Ultra-Low Power Asynchronous CMOS SRAM
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メーカー  NANOAMP [NanoAmp Solutions, Inc.]
ホームページ  http://www.nanoamp.com
Logo NANOAMP - NanoAmp Solutions, Inc.

N02L163WN1AT2-55I データシート(HTML) 3 Page - NanoAmp Solutions, Inc.

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(DOC# 14-02-014 REV L ECN# 01-1000)
3
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
NanoAmp Solutions, Inc.
N02L163WN1A
Functional Block Diagram
Functional Description
CE
WE
OE
UB
LB
I/O0 - I/O151
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7
are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown.
MODE
POWER
H
X
XXX
High Z
Standby2
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
Standby
L
X
X
H
H
High Z
Active
Active
LL
X3
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
L1
L1
Data In
Write3
Active
LH
L
L1
L1
Data Out
Read
Active
L
H
H
X
X
High Z
Active
Active
Capacitance1
1. These parameters are verified in device characterization and are not 100% tested
Item
Symbol
Test Condition
Min
Max
Unit
Input Capacitance
CIN
VIN = 0V, f = 1 MHz, TA = 25oC
8pF
I/O Capacitance
CI/O
VIN = 0V, f = 1 MHz, TA = 25oC
8pF
Address
Inputs
A0 - A3
Address
Inputs
A4 - A16
Word
Address
Decode
Logic
32K Page
x 16 word
x 16 bit
RAM Array
Input/
Output
Mux
and
Buffers
Page
Address
Decode
Logic
Control
Logic
CE
WE
OE
UB
LB
I/O0 - I/O7
I/O8 - I/O15


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