データシートサーチシステム |
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74LVQ280 データシート(PDF) 1 Page - STMicroelectronics |
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74LVQ280 データシート(HTML) 1 Page - STMicroelectronics |
1 / 8 page 1/8 July 2001 s HIGH SPEED: tPD = 8 ns (TYP.) at VCC = 3.3 V s COMPATIBLE WITH TTL OUTPUTS s LOW POWER DISSIPATION: ICC = 2µA(MAX.) at TA=25°C s LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V s 75 Ω TRANSMISSION LINE DRIVING CAPABILITY s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V s PCI BUS LEVELS GUARANTEED AT 24 mA s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 280 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74LVQ280 is a low voltage CMOS 9 BIT PARITY GENERATOR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. It is composed of nine data inputs (A to I) and odd/ even parity outputs ( ΣODD and ΣEVEN). The nine data inputs control the output conditions. When the number of high level input is odd, ΣODD output is kept high and ΣEVEN output low. Conversely, when the number of high level is even, ΣEVEN output is kept high and ΣODD low. The IC generates either odd or even parity making it flexible application. The word-length capability is easily expanded by cascading. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74LVQ280 9 BIT PARITY GENERATOR PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE TUBE T & R SOP 74LVQ280M 74LVQ280MTR TSSOP 74LVQ280TTR TSSOP SOP |
同様の部品番号 - 74LVQ280 |
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同様の説明 - 74LVQ280 |
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