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SDA525X-2 データシート(PDF) 15 Page - Siemens Semiconductor Group |
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SDA525X-2 データシート(HTML) 15 Page - Siemens Semiconductor Group |
15 / 23 page SDA 525X-2 Semiconductor Group 15 1998-10-08 of external XDATA-memory will be possible, controlled by A16, A17, A18. This offers a maximum of flexibility for 128-page-acquisition (see separate application note). 6.6 No UART As described already in the errata sheet 03/97, release 1.0, the newer versions of the SDA 525x and the SDA 525x-2 will not support a serial port (UART) any more. 6.7 VS Sampling The internal sampling time of the vertical sync pulse coming from either the VS pin or from the sandcastle signal applied at the pin HS/SC is most important for a stable display. Because the VSYNC inside a TV set is often delayed by external components, the real relation-chip of the VS-phase and the appropriate picture frame may get lost. The sampling time of the SDA 525x is derived from an internal display signal which can only be modified by programming different horizontal offset values (DHD-Register). This has the side-effect that depending on the desired horizontal offset the sampling point is also varied and may show an unstable display. To avoid this dependency, the SDA 525x-2 has a separate register to determine the VS sampling point with respect to the HS pulse, which may be varied over a whole line in steps of 8 µs. External components for VS delaying are no more necessary and can be removed if the programmed VS sampling points fits to the external timing between HS, VS and the actual frame (even/odd). To get a better timing resolution in 100 Hz-applications a special bit has been implemented to reduce the intervals between the possible sampling points from 8 to 4 µs. The register bits are described below. The following diagram shows the internal VS processing in principle. Figure 6 Internal VS Processing HS VS Sample Point Sampled VS Field Internal VS UED11012 |
同様の部品番号 - SDA525X-2 |
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同様の説明 - SDA525X-2 |
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