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AM29BDD160G データシート(PDF) 4 Page - Advanced Micro Devices |
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AM29BDD160G データシート(HTML) 4 Page - Advanced Micro Devices |
4 / 80 page 2 Am29BDD160G GENERAL DESCRIPTION The Am29BDD160 is a 16 Megabit, 2.5 Volt-only sin- gle power supply burst mode flash memory device. The device can be configured for either 1,048,576 words in 16-bit mode or 524,288 double words in 32-bit mode. The device can also be programmed in standard EPROM programmers. The device offers a configurable burst interface to 16/32-bit micropro- cessors and microcontrollers. To eliminate bus contention, each device has sepa- rate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Additional control in- puts are required for synchronous burst operations: Load Burst Address Valid (ADV#), and Clock (CLK). Each device requires only a single 2.5 or 2.6 Volt power supply (2.5 V to 2.75 V) for both read and write functions. A 12.0-volt V PP is not required for program or erase operations, al- though an acceleration pin is available if faster programming performance is required. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. The software command set is compatible with the command sets of the 5 V Am29F and 3 V Am29LV Flash families. Commands are written to the com- mand register using standard microprocessor write timing. Register contents serve as inputs to an inter- nal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the program- ming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. The Unlock Bypass mode facilitates faster pro- gramming times by requiring only two write cycles to program data instead of four. The Simultaneous Read/Write architecture pro- vides simultaneous operation by dividing the memory space into two banks. The device can begin programming or erasing in one bank, and then si- multaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. See Simultaneous Read/Write Operations Overview and Restrictions on page 13. The device provides a 256-byte SecSi™ (Secured Silicon) Sector with an one-time-programmable (OTP) mechanism. In addition, the device features several levels of sec- tor protection, which can disable both the program and erase operations in certain sectors or sector groups: Persistent Sector Protection is a com- mand sector protection method that replaces the old 12 V controlled protection method; Password Sec- tor Protection is a highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted; WP# Hardware Protection prevents program or erase in the two outermost 8 Kbytes sectors of the larger bank. The device defaults to the Persistent Sector Protec- tion mode. The customer must then choose if the Standard or Password Protection method is most de- sirable. The WP# Hardware Protection feature is always available, independent of the other protection method chosen. The Versatile I/O™ (V CCQ) feature allows the output voltage generated on the device to be determined based on the V IO level. This feature allows this device to operate in the 1.8 V I/O environment, driving and receiving signals to and from other 1.8 V devices on the same bus. In addition, inputs and I/Os that are driven ex- ternally are capable of handling 3.6 V. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, by reading the DQ7 (Data# Polling), or DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The de- vice is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write operations during power transitions. The password and software sector protection feature disables both program and erase opera- tions in any combination of sectors of memory. This can be achieved in-system at V CC level. The Program/Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any opera- tion in progress and resets the internal state machine to reading array data. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly re- duced in both these modes. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunnel- ling. The data is programmed using hot electron injection. |
同様の部品番号 - AM29BDD160G |
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同様の説明 - AM29BDD160G |
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