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AD5231BRU50-REEL7 データシート(PDF) 6 Page - Analog Devices |
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AD5231BRU50-REEL7 データシート(HTML) 6 Page - Analog Devices |
6 / 14 page PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233 REV PrF 6 22 MAR '01 Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com AD5233 PIN CONFIGURATION O1 CLK SDI SDO GND VSS A1 W1 B1 A2 W2 B2 O2 RDY CS CS CS CS PR PR PR PR WP WP WP WP VDD A4 W4 B4 A3 W3 B3 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 AD5233 PIN FUNCTION DESCRIPTION # Name Description 1 O1 Non-Volatile Digital Output #1, ADDR(O1) = 4H, data bit position D0. 2 CLK Serial Input Register clock pin. Shifts in one bit at a time on positive clock CLK edges. 3 SDI Serial Data Input Pin. 4 SDO Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands 9 & 10 activate the SDO output. See Instruction operation Truth Table. Other commands shift out the previously loaded bit pattern delayed by 16 clock pulses. This allows daisy-chain operation of multiple packages. 5 GND Ground pin, logic ground reference 6 VSS Negative Supply. Connect to zero volts for single supply applications. 7 A1 A terminal of RDAC1. 8 W1 Wiper terminal of RDAC1, ADDR(RDAC1) = 0H. 9 B1 B terminal of RDAC1. 10 A2 A terminal of RDAC2. 11 W2 Wiper terminal of RDAC2, ADDR(RDAC2) = 1H. 12 B2 B terminal of RDAC2. 13 B3 B terminal of RDAC3. 14 W3 Wiper terminal of RDAC3, ADDR(RDAC3) = 2H. 15 A3 A terminal of RDAC3. 16 B4 B terminal of RDAC4. 17 W4 Wiper terminal of RDAC4, ADDR(RDAC4) = 3H. 18 A4 A terminal of RDAC4. 19 VDD Positive Power Supply Pin. Should be ≥ the input-logic HIGH voltage. 20 WP Write Protect Pin. When active low, WP prevents any changes to the present contents, except retrieving EEMEM content and RESET. 21 PR Hardware over ride preset pin. Refreshes the scratch pad register with current contents of the EEMEM register. Factory default loads midscale 20H until EEMEM loaded with a new value by the user ( PR is activated at the logic high transition). 22 CS Serial Register chip select active low. Serial register operation takes place when CS returns to logic high. 23 RDY Ready. Active-high open drain output. Identifies completion of commands 2, 3, 8, 9, 10. 24 O2 Non-Volatile Digital Output #2, ADDR(O2) = 4H, data bit position D1. |
同様の部品番号 - AD5231BRU50-REEL7 |
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同様の説明 - AD5231BRU50-REEL7 |
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