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GD5F2GQ4RFZIS データシート(PDF) 38 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD5F2GQ4RFZIS データシート(HTML) 38 Page - GigaDevice Semiconductor (Beijing) Inc. |
38 / 57 page SPI(x1/x2/x4) NAND Flash 2G 38 13.2 Hardware Reset 13.2.1 Reset Function Description The RESET# pin allows the device to be reset by the host controller or system reset timer like watchdog for re-boot without a power off and on sequence. For the LGA8 package, pin7 can be configured as a RESET# pin depending on the status register setting, QE=0 and HOLD/RST=1(see Section Hardware RESET Setting). On the BGA24 package, a dedicated RESET# pin is provided and it is independent of QE bit setting (see Section Hardware RESET Setting). The RESET# pin goes low for a period of tRLRH or longer will reset the flash memory. After a reset cycle, the flash is at the following states: -In standby mode -All the volatile bits return to the default value as after power-on-reset. -Data of page0/block0 is read out to the cache, user can issue read from cache command (03/0B/3B/6B/BB/EB) for data. Please note that no command can be accepted during the reset cycle. (tRB1 or tRB2). Figure5-3. Hardware RESET Timing Table13-1. Hardware RESET Timing Symbol Parameter Setup Speed Unit. tRLRH Reset pulse width MIN 500 us tRHSL Reset high time before read MIN 50 ns tRB1 Reset recovery time (For NOT busy mode) MAX 500 us tRB2 Reset recovery time (For busy mode) MAX 1 ms |
同様の部品番号 - GD5F2GQ4RFZIS |
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同様の説明 - GD5F2GQ4RFZIS |
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