データシートサーチシステム |
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GD25B127D データシート(PDF) 8 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25B127D データシート(HTML) 8 Page - GigaDevice Semiconductor (Beijing) Inc. |
8 / 65 page 3.3V Uniform Sector Dual and Quad Serial Flash GD25B127D 8 4. DEVICE OPERATION SPI Mode Standard SPI The GD25B127D features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. Dual SPI The GD25B127D supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the device at twice the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1. Quad SPI The GD25B127D supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast Read”, “Quad I/O Word Fast Read” (6BH,EBH,E7H)commands. These commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1. |
同様の部品番号 - GD25B127D |
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同様の説明 - GD25B127D |
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