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データシートサーチシステム |
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データシートサーチシステム |
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GD25B256D データシート(PDF) 50 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25B256D データシート(HTML) 50 Page - GigaDevice Semiconductor (Beijing) Inc. |
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50 / 82 page  3.3V Uniform Sector Dual and Quad Serial Flash GD25B256D 50 7.25. Clear SR Flags (30H) The Clear Status Register Flags command resets bit S18 (Program Error bit) and S19 (Erase Error bit) from status register. It is not necessary to set the WEL bit before the Clear Status Register command is executed. The Clear SR command will not be accepted when the device remains busy with WIP set to 1. The WEL bit will be unchanged after this command is executed. Figure 56 Clear Status Register Flags Sequence Diagram 7.26. Release from Deep Power-Down and Read Device ID (RDI) (ABH) The Release from Power-Down and Read Device ID command is a multi-purpose command. It can be used to release the device from the Power-Down state or obtain the devices electronic identification (ID) number. To release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown below. Release from Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other c omma nd are accepted. The CS# pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy Byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown below. The Device ID value is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The command is completed by driving CS# high. When used to release the device from the Power-Down state and obtain the Device ID, the command is the same as previously described, except that after CS# is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other command will be accepted. If the Release from Power-Down / Device ID command is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle. Figure 57 Release Power-Down Sequence Diagram Command 0 1 2 3 4 5 6 7 30H CS# SCLK SI SO High-Z Command 0 1 2 3 4 5 6 7 ABH CS# SCLK SI RES1 Stand-by mode Deep Power-down mode t |
同様の部品番号 - GD25B256D |
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同様の説明 - GD25B256D |
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