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GD25D80C データシート(PDF) 16 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25D80C データシート(HTML) 16 Page - GigaDevice Semiconductor (Beijing) Inc. |
16 / 42 page 3.3V Uniform Sector Standard and Dual Serial Flash GD25D80C 16 7.7. Dual Output Fast Read (3BH) The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, and each bit being latched in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure7. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure7. Dual Output Fast Read Sequence Diagram Command 0 1 2 3 4 5 6 7 3BH CS# SCLK SI SO High-Z 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24-bit address MSB 34 35 36 37 33 5 3 1 7 5 3 1 38 39 Data Out1 32 42 43 44 45 41 46 47 40 7 Data Out2 CS# SCLK SI SO MSB Dummy Clocks 4 2 0 6 4 2 0 6 6 7 |
同様の部品番号 - GD25D80C |
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同様の説明 - GD25D80C |
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