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8XC152JB データシート(PDF) 7 Page - Intel Corporation

部品番号 8XC152JB
部品情報  UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER
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メーカー  INTEL [Intel Corporation]
ホームページ  http://www.intel.com
Logo INTEL - Intel Corporation

8XC152JB データシート(HTML) 7 Page - Intel Corporation

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8XC152JAJBJCJD
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output respec-
tively of an inverting amplifier which can be config-
ured for use as an on-chip oscillator as shown in
Figure 3
To drive the device from an external clock source
XTAL1 should be driven while XTAL2 is left uncon-
nected as shown in Figure 4 There are no require-
ments on the duty cycle of the external clock signal
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop but minimum and
maximum high and low times specified on the Data
Sheet must be observed
An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts-up This is due
to interaction between the amplifier and its feedback
capacitance Once the external signal meets the VIL
and VIH specifications the capacitance will not ex-
ceed 20 pF
270431 – 5
Figure 3 Using the On-Chip Oscillator
270431 – 6
Figure 4 External Clock Drive
IDLE MODE
In Idle Mode the CPU puts itself to sleep while most
of the on-chip peripherals remain active The major
peripherals that do not remain active during Idle are
the DMA channels The Idle Mode is invoked by
software The content of the on-chip RAM and all
the Special Function Registers remain unchanged
during this mode The Idle Mode can be terminated
by any enabled interrupt or by a hardware reset
POWER DOWN MODE
In Power Down Mode the oscillator is stopped and
all on-chip functions cease except that the on-chip
RAM contents are maintained The mode Power
Down is invoked by software The Power Down
Mode can be terminated only by a hardware reset
Table 3 Status of the External Pins During Idle and Power Down Modes
80C152JA83C152JA80C152JC83C152JC
Mode
Program
ALE
PSEN
Port 0
Port 1
Port 2
Port 3
Port 4
Memory
Idle
Internal
1
1
Data
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Data
Power Down
Internal
0
0
Data
Data
Data
Data
Data
Power Down
External
0
0
Float
Data
Data
Data
Data
80C152JB80C152JD
Mode
Instruction
ALE PSEN EPSEN Port 0 Port 1
Port 2
Port 3 Port 4 Port 5
Port 6
Bus
Idle
P0 P2
1
1
1
Float
Data
Address
Data
Data
0FFH
0FFH
Idle
P5 P6
1
1
1
Data
Data
Data
Data
Data
0FFH Address
Power Down
P0 P2
0
0
1
Float
Data
Data
Data
Data
0FFH
0FFH
Power Down
P5 P6
0
1
0
Data
Data
Data
Data
Data
0FFH
0FFH
NOTE
For more detailed information on the reduced power modes refer to the Embedded Controller Handbook and Application
Note AP-252 ‘‘Designing with the 80C51BH’’
Note difference of logic level of PSEN during Power Down for ROM JAJC and ROM emulation mode for JCJD
7


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