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MC100SX1230 データシート(PDF) 4 Page - ON Semiconductor

部品番号 MC100SX1230
部品情報  CMI CODER/DECODER
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MC100SX1230 データシート(HTML) 4 Page - ON Semiconductor

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MC100SX1230
4
MOTOROLA
High Performance Frequency
Control Products — BR1334
Applications Information
CMI Code
The CMI code is a 1B2B code. Each information bit is
coded into two transmission bits. A binary 0 is coded to 01,
and a binary 1 is coded alternately to a 00 or a 11, thus there
is at least one transition during every bit period. A typical
data pattern is illustrated in the figure below. Because of the
coding, the data stream is not only DC balanced, but it
contains a rich clock component which aids the clock
recovery process at the receiver. A 2X clock is used by the
MC100SX1230 to ensure that the mid-bit transition of the
data 0 is ideally centered at the CMI encoded output.
Figure 1. CMI Code
Binary
CMI
001
10
001
10
Typical Application
In a traditional telecommunications application, the
MC100SX1230 is resident on the line card interface which
contains circuitry to implement the line transmitter and
receiver functions. On the decoder side, a cable equalization
filter followed by a clock recovery/decision circuit are
required to compensate for the cable attenuation and
distortion, extract the 2X clock signal and re-time the CMI
data. On the coder side, a PLL is required to synthesize the
2X coder clock and a conditioning circuit is needed at the
output of the coder to generate the appropriate signal to drive
the cable.
Device Operation
The circuit contains a complete CMI coder and decoder as
well as the support circuitry necessary to perform loop back
of either the Binary input or the CMI input. The operation is
controlled by the LCMI and LBIN inputs. In addition, the
device generates an AIS (Alarm Indication Signal) from the
coder output when the binary loop back state is active
(LBIN=‘H’). The AIS signal indicates to the receiver at the
other end of the cable that ‘real’ data is not being sent. The
device contains a Reset input which should normally be reset
as part of the powering up sequence.
The coder accepts a differential data input (BINin) as well
as a differential clock (CCLKin). The clock signal must be
twice the frequency of the input data signal, i.e. a 155 MBit/s
binary signal requires a 310 MHz clock, for proper operation.
Typical input and output waveforms are shown in Figure 2.
The incoming clock signal is divided by 2 and supplied at the
coder clock output (CLKout). The BINin signal is buffered
before being driven into the input register which clocks in the
binary data. This results in a negative setup time for the
coder. The coded data is output from the coder 3 CCLKin
clock cycles plus normal propagation delay after the binary
data has been supplied.
The decoder accepts a differential data input (CMIin) as
well as a differential clock (DCLKin). The clock signal is
supplied from the external clock extraction circuit and runs at
the coded rate of either 280 MHz or 310 MHz depending on
weather the application is for a PDH system or an SDH
system. The decoder has a latency of 4 clock cycles so the
decoded data is output 4 cycles plus the normal propagation
delay after the input data is captured. Figure 3 illustrates the
decoder operation.
Under certain conditions, the user may require that the
binary data to be coded be routed back to the output of the
decoder to verify proper system operation. This is accom-
plished through the use of the LBIN input control pin. When
this signal is asserted (LBIN = ‘H’), the BINin signal as well
as a divided by 2 version of the CCLKin input is routed to the
QBIN and DCLKout outputs respectively. The BINin to QBIN
output has a latency of 3 CCLKin cycles plus internal
propagation delays. In addition, the AIS signal is generated
and output from the QCMI output. To the receiver the AIS
signal is decoded as a constant logic ‘H’ signal. This
operation is seen in Figure 4.
To complement the binary loop back feature, a CMI loop
back function is also supported. This is accomplished by
asserting the LCMI input control pin (LCMI =‘H’). Under this
condition, the CMI coded input is decoded, then routed
through the coder block to the QCMI output. The CMIin to
QCMI output has a latency of 5 DCLKin cycles plus internal
propagation delays. Figure 5 shows the CMI loop back
operation.


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