FM24C16A
Rev 0.1
June 2002
Page 7 of 13
command to be issued with the slave address set to 1.
The operation is now a current address read. This
operation is illustrated in Figure 9.
S
A
Slave Address
1
Data Byte
1
P
By Master
By FM24C16
Start
Address
Stop
Acknowledge
No
Acknowledge
Data
Figure 7. Current Address Read
S
A
Slave Address
1
Data Byte
1
P
By Master
By FM24C16
Start
Address
Stop
Acknowledge
No
Acknowledge
Data
Data Byte
A
Acknowledge
Figure 8. Sequential Read
S
A
Slave Address
1
Data Byte
1
P
By Master
By FM24C16
Start
Address
Stop
No
Acknowledge
Data
Data Byte
A
Acknowledge
S
A
Slave Address
0
Word Address
A
Start
Address
Acknowledge
Figure 9. Selective (Random) Read
Endurance
The FM24C16A internally operates with a read and
restore mechanism. Therefore, endurance cycles are
applied for each read or write cycle. The FRAM
architecture is based on an array of rows and
columns. Rows are defined by A10-A3. Each access
causes an endurance cycle for a row. Endurance can
be optimized by ensuring frequently accessed data is
placed in different rows. Regardless, FRAM read and
write endurance is effectively unlimited at the 1MHz
two-wire speed. Even at 3000 accesses per second to
the same row, 10 years time will elapse before 1
trillion endurance cycles occur.
Applications
The versatility of FRAM technology fits into many
diverse applications. Clearly the strength of higher
write endurance and faster writes make FRAM
superior
to
EEPROM
in
all
but
one-time
programmable applications. The advantage is most
obvious in data collection environments where writes
are frequent and data must be nonvolatile.
The attributes of fast writes and high write endurance
combine in many innovative ways. A short list of
ideas is provided here.
1.
Data collection. In applications where data is
collected and saved, FRAM provides a superior
alternative to other solutions. It is more cost effective
than battery backup for SRAM and provides better
write attributes than EEPROM.
2.
Configuration. Any nonvolatile memory can
retain a configuration. However, if the configuration
changes and power failure is a possibility, the higher
write endurance of FRAM allows changes to be
recorded without restriction. Any time the system