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PCI7610 データシート(PDF) 70 Page - Texas Instruments |
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PCI7610 データシート(HTML) 70 Page - Texas Instruments |
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70 / 240 page  3−28 3.9.10 CardBus Bridge Power Management The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges was approved by PCMCIA in December of 1997. This specification follows the device and bus state definitions provided in the PCI Bus Power Management Interface Specification published by the PCI Special Interest Group (SIG). The main issue addressed in the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges is wake-up from D3hot or D3cold without losing wake-up context (also called PME context). The specific issues addressed by the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges for D3 wake-up are as follows: • Preservation of device context. The specification states that a reset must occur during the transition from D3 to D0. Some method to preserve wake-up context must be implemented so that the reset does not clear the PME context registers. • Power source in D3cold if wake-up support is required from this state. The Texas Instruments PCI7610 controller addresses these D3 wake-up issues in the following manner: • Two resets are provided to handle preservation of PME context bits: − Global reset (GRST) is used only on the initial boot up of the system after power up. It places the PCI7610 controller in its default state and requires BIOS to configure the controller before becoming fully functional. − PCI reset (PRST) has dual functionality based on whether PME is enabled or not. If PME is enabled, then PME context is preserved. If PME is not enabled, then PRST acts the same as a normal PCI reset. Please see the master list of PME context bits in Section 3.9.12. • Power source in D3cold if wake-up support is required from this state. Since VCC is removed in D3cold, an auxiliary power source must be supplied to the PCI7610 VCC terminals. Consult the PCI14xx Implementation Guide for D3 Wake-Up or the PCI Power Management Interface Specification for PCI to CardBus Bridges for further information. 3.9.11 ACPI Support The Advanced Configuration and Power Interface (ACPI) Specification provides a mechanism that allows unique pieces of hardware to be described to the ACPI driver. The PCI7610 controller offers a generic interface that is compliant with ACPI design rules. Two doublewords of general-purpose ACPI programming bits reside in PCI7610 PCI configuration space at offset 88h. The programming model is broken into status and control functions. In compliance with ACPI, the top level event status and enable bits reside in the general-purpose event status register (PCI offset 88h, see Section 4.33) and general-purpose event enable register (PCI offset 89h, see Section 4.34). The status and enable bits are implemented as defined by ACPI and illustrated in Figure 3−17. Event Output Event Input Enable Bit Status Bit Figure 3−17. Block Diagram of a Status/Enable Cell The status and enable bits generate an event that allows the ACPI driver to call a control method associated with the pending status bit. The control method can then control the hardware by manipulating the hardware control bits or by investigating child status bits and calling their respective control methods. A hierarchical implementation would be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report events. For more information of ACPI, see the Advanced Configuration and Power Interface (ACPI) Specification. |
同様の部品番号 - PCI7610 |
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同様の説明 - PCI7610 |
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