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LMS7002M データシート(PDF) 10 Page - List of Unclassifed Manufacturers

部品番号 LMS7002M
部品情報  FPRF MIMO Transceiver IC With Integrated Microcontroller
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LMS7002M
10
LMS7002M
– FPRF MIMO Transceiver IC
Figure 25: HB2 amplitude response
Decimation
The decimation function is implemented using the same filters as in the
case for interpolation although the hardware is simplified slightly by
taking advantage of only having to provide every second sample at the
sub-filters output. The filter chain is shown in Figure 26.
HB2a
2
HB2b
2
HB2c
2
HB1
2
X
Y
clk2
clk3
clk4
clk5
clk1
HB2d
2
Figure 26: Programmable rate decimation
implemented by half band filters
Decimation ratio K can be programmed to be:
32
or
16
,
8
,
4
,
2
,
1
K
.
Decimation by 1 is achieved by bypassing all the decimation filters.
Decimator performance is the same as the performance of the
interpolator i.e. pass band is:
K
f
x
f
clk
p
.
In this case fclk is RXTSP i.e. ADCs clock frequency. As before, scaling
factor x in the equation above, for K=2, 4, 8, 16, 32, should be set to
one of the following values:
x <= 0.27 for >= 108dB decimation alias suppression,
x <= 0.30 for >= 75dB decimation alias suppression,
x <= 0.32 for >= 60dB decimation alias suppression.
Again, x can be used to trade off decimation alias suppression for the
decimation filter pass band.
For K=1, x should be set to x < 0.5 to limit the signal BW below Nyquist
making the room for additional filtering in BB, if required. There is no
decimation alias in this case hence more flexibility to set x for higher
IF/RF bandwidth.
In case of decimation, normalizing frequency in Figure 23 and Figure 25
is the filters input sample rate which is twice the sample rate at the
output.
General Purpose FIR Filters
The LMS7002M features general purpose filters 1 and 2, which are
based on a Multiply and Accumulate (MAC) FIR architecture. They can
implement up to a 40-tap filtering function and the coefficients are fully
programmable via SPI. The hardware implementation does not impose
the constraint for the filter impulse response to be symmetrical hence
the filter phase response can but does not need to be ideally linear.
Therefore, it can be used in general filtering, as well as in phase
nonlinear applications in which case the filter can implement phase
equalization.
The filter coefficients are stored in five 8x16-bit internal memory banks
as two’s complement signed integers as shown in Figure 27 where L is
related to the filter length N as follows:
5
N
L
.
Grey locations in Figure 27 highlight the memory registers which are set
to zero for 5L > N.
Evidently, the number of the filter taps N is limited by the size of the
coefficients memory to:
40
8
*
5
N
.
The following relationship must be satisfied:
K
L
,
K being the interpolation or decimation ratio, for the MAC hardware to
be able to produce output samples on time.
Memory Bank 0
Memory Bank 1
Memory Bank 4
Figure 27: General purpose FIR filter coefficients memory organisation
General purpose FIR filter 3 hardware is composed of three filters (each
equivalent to G.P. FIR 1 or 2) running in parallel in order to increase its
processing power. For G.P. FIR 3 the equivalent equations are as
below:
5
*
3
N
L
,
120
8
*
5
*
3
N
, and
K
L
 .
Coefficients memory is organised as in Figure 27 with memory banks
being tripled. This filter can be used as a channel select filter or for any
other purpose which requires a larger number of filtering taps.
Received Signal Strength Indicators
A digital received signal strength indicator (RSSI) circuit calculates the
level of the received complex signal (I + jQ) as follows:
2
2
2
Q
I
RSSI
.
The following approximation of the square root is implemented in the
chip:
M
N
M
M
b
a
,
5
.
0
125
.
0
max
2
2
,
where:
 
 
b
a
N
b
a
M
,
min
,
max
.
The same RSSI block is used within the digital AGC loop. If digital AGC
is not required then the RSSI output, after being averaged by the
COMB filter, can be provided back to the BB modem via SPI as shown
in Figure 28. In this way the BB can control RF and IF gain stages to
implement analog AGC in which case the AGC loop is closed via the
BB modem.
There is also an RF RSSI block implemented in the RF front end
connected to the input of the wideband LNA, see Figure 1. This block


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