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LT8920 データシート(PDF) 40 Page - List of Unclassifed Manufacturers

部品番号 LT8920
部品情報  Long range 2.4GHz Radio Transceiver
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LT8920 データシート(HTML) 40 Page - List of Unclassifed Manufacturers

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LT8920 Datasheet V1.1
Page 40
Jan. 2017
11.8.2. FW_TERM_TX= 0 (Transmit)
When Register 41[13:12] = ‘b00, the LT8910 framer does not stop packet transmission until MCU/application
writes Register 7[8] TX_EN bit = 0. Packet transmission continues even if FIFO is empty. The timing diagram
is shown in Figure below.
Figure 13.
TX timing diagram when Register 41[13:12] = ‘b00.
PKT and FIFO flags are shown high active.
Write Reg7
SPI_SS
Internal TX on
2us
Tx on delay
PA on delay
Tx packet
Internal Tx Data
PKT_flag
FIFO_flag
PKT_flag=1 after Tx packet has been sent
MCU fills FIFO before framer sends trailer bits
FIFO_flag=1 when FIFO is empty
8us
Framer terminates TX when
MCU/Application writes Reg7 TX_EN=0
Write Reg7
2us
Note: When Register 41[13] = 0 (MCU/application handles packet length), never let FIFO underflow or over flow. FIFO full/empty
thresholds can be controlled via Register 40 FIFO_EMPTY_THRESHOLD and FIFO_FULL_THRESHOLD settings. The best value will
depend on SPI speed, and speed at which MCU/application can stream the data into FIFO.


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