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MC10ELT22 データシート(PDF) 1 Page - ON Semiconductor |
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MC10ELT22 データシート(HTML) 1 Page - ON Semiconductor |
1 / 3 page MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3–1 REV 3 © Motorola, Inc. 1996 7/96 Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. Because the mature MOSAIC 1.5 process is used, low cost can be added to the list of features. The ELT22 is available in both ECL standards: the 10ELT is compatible with positive MECL 10H logic levels while the 100ELT is compatible with positive ECL 100K logic levels. • 1.5ns Typical Propagation Delay • <300ps Typical Output to Output Skew • Differential PECL Outputs • Small Outline SOIC Package • PNP TTL Inputs for Minimal Loading • Flow Through Pinouts 1 2 3 4 5 6 7 8 D0 GND VCC LOGIC DIAGRAM AND PINOUT ASSIGNMENT Q0 D1 Q1 Q1 Q0 PECL TTL MC10ELT22 MC100ELT22 PIN FUNCTION Qn Diff PECL Outputs Dn TTL Inputs VCC +5.0V Supply GND Ground PIN DESCRIPTION 1 8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751-05 |
同様の部品番号 - MC10ELT22 |
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同様の説明 - MC10ELT22 |
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