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MC10EP105FAR2 データシート(PDF) 1 Page - ON Semiconductor |
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MC10EP105FAR2 データシート(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 0 1 Publication Order Number: MC10EP105/D MC10EP105 Product Preview Quad 2-Input Differential AND/NAND The MC10EP105 is a 2–input differential AND/NAND gate. Each gate is functionally equivalent to a EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. • 190ps Typical Propagation Delay • High Bandwidth to 3 Ghz Typical • ECL mode: 0V VCC with VEE = –3.0V to –5.5V • PECL mode: 3.0V to 5.5V VCC with VEE = 0V • Internal Input Pulldown Resistors • ESD Protection: >2KV HBM, >100V MM • New Differential Input Common Mode Range • Moisture Sensitivity Level 2 For Additional Information, See Application Note AND8003/D • Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34 • Transistor Count = 444 devices LOGIC DIAGRAM D0a D0a D0b D0b Q0 Q0 D1a D1a D1b D1b Q1 Q1 D2a D2a D2b D2b Q2 Q2 D3a D3a D3b D3b Q3 Q3 This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. PIN DESCRIPTION PIN Dna, Dnb, Dna, Dnb Qn, Qn ECL Data Outputs FUNCTION ECL Data Inputs http://onsemi.com Dna Dnb Dna Dnb Qn Qn LL H H L H LH H L L H HL L H L H HH L L H L TRUTH TABLE 32–LEAD TQFP FA SUFFIX CASE 873A MARKING DIAGRAM* MC10 AWLYYWW 1 32 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week *For additional information, see Application Note AND8002/D EP105 Device Package Shipping ORDERING INFORMATION MC10EP105FA TQFP 250 Units/Tray MC10EP105FAR2 TQFP 2000 Tape & Reel VBB VCC Positive Supply Reference Voltage Output VEE Negative, 0 Supply |
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