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MC14553BDW データシート(PDF) 1 Page - ON Semiconductor |
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MC14553BDW データシート(HTML) 1 Page - ON Semiconductor |
1 / 12 page © Semiconductor Components Industries, LLC, 2000 March, 2000 – Rev. 3 1 Publication Order Number: MC14553B/D MC14553B 3-Digit BCD Counter The MC14553B 3–digit BCD counter consists of 3 negative edge triggered BCD counters that are cascaded synchronously. A quad latch at the output of each counter permits storage of any given count. The information is then time division multiplexed, providing one BCD number or digit at a time. Digit select outputs provide display control. All outputs are TTL compatible. An on–chip oscillator provides the low–frequency scanning clock which drives the multiplexer output selector. This device is used in instrumentation counters, clock displays, digital panel meters, and as a building block for general logic applications. • TTL Compatible Outputs • On–Chip Oscillator • Cascadable • Clock Disable Input • Pulse Shaping Permits Very Slow Rise Times on Input Clock • Output Latches • Master Reset MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) Symbol Parameter Value Unit VDD DC Supply Voltage Range – 0.5 to +18.0 V Vin, Vout Input or Output Voltage Range (DC or Transient) – 0.5 to VDD + 0.5 V Iin Input Current (DC or Transient) per Pin ±10 mA Iout Output Current (DC or Transient) per Pin +20 mA PD Power Dissipation, per Package (Note 2.) 500 mW TA Ambient Temperature Range – 55 to +125 °C Tstg Storage Temperature Range – 65 to +150 °C TL Lead Temperature (8–Second Soldering) 260 °C 1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/ _C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. http://onsemi.com A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week Device Package Shipping ORDERING INFORMATION MC14553BCP PDIP–16 25/Rail MC14553BDW SOIC–16 47/Rail MARKING DIAGRAMS 1 16 PDIP–16 P SUFFIX CASE 648 MC14553BCP AWLYYWW SOIC–16 DW SUFFIX CASE 751G 1 16 14553B AWLYYWW |
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