KM416S1021CT-G7 datasheet(5/8 Pages) SAMSUNG

部品番号	KM416S1021CT-G7

部品情報	512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface

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メーカー	SAMSUNG [Samsung semiconductor]

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KM416S1021C

REV. 1. May '98

CMOS SDRAM

Preliminary

OPERATING AC PARAMETER(AC operating conditions unless otherwise noted)

Parameter

Symbol

Version

Unit

Note

-7

-S

-8

Row active to row active delay

tRRD(min)

14

20

16

ns

1

RAS to CAS delay

tRCD(min)

21

20

24

ns

1

Row precharge time

tRP(min)

21

20

24

ns

1

Row active time

tRAS(min)

49

50

56

ns

1

tRAS(max)

100

us

Row cycle time

tRC(min)

70

80

ns

1

Last data in to new col. address delay

tCDL(min)

1

CLK

2

Last data in to row precharge

tRDL(min)

1

CLK

2

Last data in to burst stop

tBDL(min)

1

CLK

2

Col. address to col. address delay

tCCD(min)

1

CLK

3

Number of valid output data

CAS latency=3

2

-

2

ea

4

CAS latency=2

1

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

Notes :

Vtt = 0.45 * VDDQ

50

Ω

Output

CLOAD=30pF

Z0 = 50

Ω

(Fig. 1) Output load circuit

AC OPERATING TEST CONDITIONS(VDD = 3.3V

± 0.3V, 3.43V ± 0.5%, TA = 0 to 70°C)

Parameter

Value

Unit

Input reference voltage

0.45 * VDDQ

V

Input signal maximum peak swing

2.0

V

Inout signal minimum slew rate

1.0

V/ns

AC input levels (Vih/Vil)

VREF+0.4/VREF-0.4

V

Input timing measurement reference level

VREF

V

Output timing measurement reference level

Vtt

V

Output load condition

See Fig. 1

VREF = 0.45 * VDDQ

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