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Rev: 1.06 6/2000
8/15
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116TP/J/U
Read Cycle 2: WE = VIH
* These parameters are sampled and are not 100% tested
Write Cycle
Parameter
Symbol
-10
-12
-15
Unit
Min
Max
Min
Max
Min
Max
Write cycle time
tWC
10
---
12
---
15
---
ns
Address valid to end of write
tAW
7
---
8
---
10
---
ns
Chip enable to end of write
tCW
7
---
8
---
10
---
ns
Byte enable to end of write
tBW
7
---
8
---
10
---
ns
Data set up time
tDW
5
---
6
---
7
---
ns
Data hold time
tDH
0
---
0
---
0
---
ns
Write pulse width
tWP
7
---
8
---
10
---
ns
Address set up time
tAS
0
---
0
---
0
---
ns
Write recovery time (WE)
tWR
0
---
0
---
0
---
ns
Write recovery time (CE)
tWR1
0
---
0
---
0
---
ns
Output Low Z from end of write
tWLZ*
3
---
3
---
3
---
ns
Write to output in High Z
tWHZ*
---
4
---
5
---
6
ns
tAA
tRC
Address
tAC
tLZ
tAB
tBLZ
tOE
tOLZ
CE
UB, LB
OE
Data Out
tHZ
tBHZ
tOHZ
Data valid
High impedance