FM24C256
Rev 1.3
Feb. 2004
Page 8 of 13
Endurance
A FRAM internally operates with a read and restore
mechanism. Therefore, endurance cycles are applied
for
each read
and write access. The FRAM
architecture is based on an array of rows and
columns. Rows (A14-A6) are subdivided into 8
segments (A5-A3). Each access causes an endurance
cycle for a row segment. In the FM24C256, there are
8 bytes per segment. Endurance can be optimized by
ensuring frequently accessed data is located in
different segments. Regardless, FRAM read and
write endurance is effectively unlimited at the 1MHz
two-wire speed. Even at 30 accesses per second to
the same segment, 10 years time will elapse before
10 billion endurance cycles occur.
Applications
The versatility of FRAM technology fits into many
diverse applications. Clearly the strength of higher
write endurance and faster writes make FRAM
superior
to
EEPROM
in
all
but
one-time
programmable applications. The advantage is most
obvious in data collection environments where writes
are frequent and data must be nonvolatile.
The attributes of fast writes and high write endurance
combine in many innovative ways. A short list of
ideas is provided here.
1.
Data collection. In applications where data is
collected and saved, FRAM provides a superior
alternative to other solutions. It is more cost effective
than battery backup for SRAM and provides better
write attributes than EEPROM.
2.
Configuration. Any nonvolatile memory can
retain a configuration. However, if the configuration
changes and power failure is a possibility, the higher
write endurance of FRAM allows changes to be
recorded without restriction. Any time the system
state is altered, the change can be written. This avoids
writing to memory on power down when the
available time is short and power scarce.
3.
High noise environments. Writing to EEPROM
in a noisy environment can be challenging. When
severe noise or power fluctuations are present, the
long write time of EEPROM creates a window of
vulnerability
during
which
the
write
can
be
corrupted. The fast write of FRAM is complete
within a microsecond. This time is typically fast
enough to avoid noise or power supply disturbances.
4.
Time to market. In a complex system, multiple
software routines may need to access the nonvolatile
memory.
In
this
environment
the
time
delay
associated with programming EEPROM adds undue
complexity to the software development. Each
software
routine
must
wait
for
complete
programming before allowing access to the next
routine. When time to market is critical, FRAM can
eliminate this obstacle. As soon as a write is issued to
the FM24C256, it is effectively done -- no waiting.
5.
RF/ID. In the area of contactless memory,
FRAM provides an ideal solution. Since RF/ID
memory is powered by an RF field, the long
programming time and high current consumption
needed to write EEPROM is unattractive. FRAM
provides a superior solution. The FM24C256 is
suitable for multi-chip RF/ID products.
6.
Maintenance tracking. In sophisticated systems,
the operating history and system state must be
captured prior to a failure. Maintenance can be
expedited when this information has been recorded
frequently. Due to the high write endurance, FRAM
makes
an
ideal
system log.
In
addition,
the
convenient 2-wire interface of the FM24C256 allows
memory to be distributed throughout the system
using minimal additional resources.