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8

ORGANISATION OF INTERRUPTIONS.

The interruptions may be initiated:

а) by external devices from bits РORT1-PORT8;

б) by internal devices (timers T1,T2,T3).

The initial addresses of subprograms of processing interruptions as their priority decrease are

shown in the table.

Address

Source of interruption

Note

0x000

Supply switching on

0x08F

Timers 1, 2 and 3 simultaneously

0x09F

Timers 2 and 3 simultaneously

0x0AF

Timers 1 and 3 simultaneously

0x0CF

Timers 1 and 2 simultaneously

0x0BF

Timer 3

0x0DF

Timer 2

0x0EF

Timer 1

Simultaneously with timers there

may be initiated interruption from

input port which should be taken

into consideration in interrupt ser-

vice routine

0x0FF

Input / output port

Interruptions are executed after complete execution of the command of main program when there

is a request. Interruptions are inhibited after the jump instructions: JMP, JMI and JC, JNC, JZ, JNZ

when executing jump conditions, commands JSR of return from subprogram.

Interruptions from port bits may be initiated if the corresponding bit of interrupt enabling register in

register RFC_2 is program-set into 1.

At the same time, reading the register RFC_3 (read-only) allows to display from which port bits

interrupt requests are called. Interrupt request from any port bit can be reset after executing inter-

rupt service routine by recording 0 into the corresponding bit in the register RFC_2 with the follow-

ing setting of this bit into 1 for enabling thhe further inmterrupt request. Each port bit can be indi-

vidually tuned by presetting bits M1, M0 in the registers RFC_3 and RFC_3 with the following pos-

sible options of internal states.

Bits

Internal

Interrupts

Notes

M1

M0

port state

0

0

OUT ZL (high-impedance 0)

By mask «programming» internal level ZL

(high-impedance 0) can be disconnected

0

1

OUT L

( “strong” zero)

Interrupts from

external actions

inhibited

1

0

IN RL (resistive 0)

Interrupts evocation under high level

1

1

IN RH

(resistive 1)

Interrupts from

external actions

enabled

Interrupts evocation under low level

Mask «programming» can disconnect internal level (ZL, RL,RH) with possible replacement of

them by external resistors.

Reading of the register R FC_4 (read-only) allows to display state of all port bits given either, one

or another external action.

External actions may be the following:

H

– «strong» 1

HR – «weak» 1

L

– «strong» 0

LR – «weak» 0

Z

– high impedance state

State of port bits under all possible combinations of external actions and internal states are shown

in the table

Internal

External action

state

H

HR

L

LR

Z

IN RH

1

1

0

0

1

IN RL

1

1

0

0

0