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FIN3385 データシート(PDF) 9 Page - Fairchild Semiconductor

部品番号 FIN3385
部品情報  Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers
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メーカー  FAIRCHILD [Fairchild Semiconductor]
ホームページ  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

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Receiver AC Electrical Characteristics (66MHz)
Note 20: For the receiver with falling-edge strobe, the definition of setup/hold time will be slightly different from the one with rising-edge strobe. The clock ref-
erence point is the time when the clock falling edge passes through 2V. For hold time tRHRC, the clock reference point is the time when falling edge passes
through
0.8V.
Note 21: Total channel latency from Sewrializer to deserializer is (T
 tTCCD)  (2*T  tRCCD). There is the clock period.
Note 22: Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
tRCOP
Receiver Clock Output (RxCLKOut) Period
See Figure 8
15.0
T
50.0
ns
tRCOL
RxCLKOut LOW Time
10.0
11.0
ns
tRCOH
RxCLKOut HIGH Time
See Figure 8
10.0
12.2
ns
tRSRC
RxOut Valid Prior to RxCLKOut
(Rising Edge Strobe)
6.5
11.6
ns
tRHRC
RxOut Valid After RxCLKOut
(f
40 MHz)
6.0
11.6
ns
tRCOL
RxCLKOut LOW Time
5.0
6.3
9.0
ns
tRCOH
RxCLKOut HIGH Time
See Figure 8, (Note 20)
5.0
7.6
9.0
ns
tRSRC
RxOut Valid Prior to RxCLKOut
(Rising Edge Strobe)
4.5
7.3
ns
tRHRC
RxOut Valid After RxCLKOut
(f
66 MHz)
4.0
6.3
ns
tROLH
Output Rise Time (20% to 80%)
CL 8 pF, (Note 20)
2.0
5.0
ns
tROHL
Output Fall Time (80% to 20%)
See Figure 8
1.8
5.0
ns
tRCCD
Receiver Clock Input to Clock Output Delay
See Figure 10, (Note 21)
3.5
5.0
7.5
ns
TA 25qC and VCC 3.3V
tRPDD
Receiver Power-Down Delay
See Figure 13
1.0
Ps
tRSPB0
Receiver Input Strobe Position of Bit 0
1.0
1.4
2.15
ns
tRSPB1
Receiver Input Strobe Position of Bit 1
4.5
5.0
5.8
ns
tRSPB2
Receiver Input Strobe Position of Bit 2
See Figure 17
8.1
8.5
9.15
ns
tRSPB3
Receiver Input Strobe Position of Bit 3
(f
40 MHz)
11.6
11.9
12.6
ns
tRSPB4
Receiver Input Strobe Position of Bit 4
15.1
15.6
16.3
ns
tRSPB5
Receiver Input Strobe Position of Bit 5
18.8
19.2
19.9
ns
tRSPB6
Receiver Input Strobe Position of Bit 6
22.5
22.9
23.6
ns
tRSPB0
Receiver Input Strobe Position of Bit 0
0.7
1.1
1.4
ns
tRSPB1
Receiver Input Strobe Position of Bit 1
2.9
3.3
3.6
ns
tRSPB2
Receiver Input Strobe Position of Bit2
See Figure 17
5.1
5.5
5.8
ns
tRSPB3
Receiver Input Strobe Position of Bit 3
(f
65 MHz)
7.3
7.7
8.0
ns
tRSPB4
Receiver Input Strobe Position of Bit 4
9.5
9.9
10.2
ns
tRSPB5
Receiver Input Strobe Position of Bit 5
11.7
12.1
12.4
ns
tRSPB6
Receiver Input Strobe Position of Bit 6
13.9
14.3
14.6
ns
tRSKM
RxIn Skew Margin
f
40 MHz
490
ps
See Figure 17, (Note 22)
f
66 MHz
400
tRPLLS
Receiver Phase Lock Loop Set Time
See Figure 11
10.0
ms


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