GS1574A Data Sheet

33416 - 5

March 2006

3 of 16

1. Pin Out

1.1 GS1574A Pin Assignment

Figure 1-1: 16-Pin QFN

1.2 GS1574A Pin Descriptions

GS1574A

(top view)

1

SDI

SDI

2

3

4

SDO

SDO

12

11

10

9

5

7

68

13

14

15

16

Center Pad

(bottom of package, internally

bonded to VEE_A)

Table 1-1: GS1574A Pin Descriptions

Pin Number

Name

Timing

Type

Description

1, 4

VEE_A

Analog

Power

Most negative power supply for analog circuitry.

Connect to GND.

2, 3

SDI, SDI

Analog

Input

Serial digital differential input.

5, 6

AGC, AGC

Analog

–

External AGC capacitor.

Connect pin 5 and pin 6 together as shown in the Typical Application

Circuit on page 13.

7

BYPASS

Not

Synchronous

Input

Forces the Equalizing and DC RESTORE stages into bypass mode

when HIGH. No equalization occurs in this mode.

8

MCLADJ

Analog

Input

Maximum cable length adjust.

Adjusts the approximate maximum amount of cable to be equalized

(from 0m to the maximum cable length). The output is muted (latched to

the last state) when the maximum cable length is achieved.

NOTE: MCLADJ is only recommended for data rates up to 360Mb/s.

For data rates above this, MCLADJ should be left floating.