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TDAT162G52 データシート(PDF) 4 Page - Agere Systems |
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TDAT162G52 データシート(HTML) 4 Page - Agere Systems |
4 / 810 page MARS2G5 P-Pro (TDAT162G52) SONET/SDH Data Sheet 155/622/2488 Mbits/s Data Interface August 18, 2004 4 Contents Page Table of Contents (continued) Agere Systems Inc. Receive .......................................................................................................................................................... 636 Transmit ......................................................................................................................................................... 639 Examples of CRC Insertion/Testing ............................................................................................................... 641 Data Engine Block—PPP Detach Subblock ......................................................................................................... 645 PPP Header Detach....................................................................................................................................... 645 Data Engine Block—Data Engine Counter Subblock ........................................................................................... 648 Introduction .................................................................................................................................................... 648 Overview ........................................................................................................................................................ 648 Implementation .............................................................................................................................................. 648 Data Engine Block—Channel Distribution and Allocation Subblock..................................................................... 651 Channel Distribution and Allocation Subblock Description ............................................................................ 651 Operation and Programming of the CDA Maps ............................................................................................. 652 Data Engine Block—GFP General Framing Procedure Subblock........................................................................668 Introduction .................................................................................................................................................... 668 Overview ........................................................................................................................................................ 668 GFP Control Messages.................................................................................................................................. 670 GFP Frame Delineation/Frame Insertion ....................................................................................................... 671 GFP Scrambling/Descrambling...................................................................................................................... 673 Packet-Over-Wavelength Mode ..................................................................................................................... 676 Data Engine Block Registers................................................................................................................................ 677 DE Register Descriptions ............................................................................................................................... 677 DE Register Map............................................................................................................................................ 703 UTOPIA (UT) Block .............................................................................................................................................. 716 UTOPIA Interface Features ........................................................................................................................... 716 UTOPIA Modes .............................................................................................................................................. 718 32-Bit Mode Configuration (Necessary Configuration for Proper Operation)................................................. 718 UT Receive Path (Ingress)............................................................................................................................. 721 UT Transmit Path (Egress) ............................................................................................................................ 724 Address Modes and Pin Assignments of MPHY Interfaces ........................................................................... 726 UTOPIA Loopbacks ....................................................................................................................................... 729 Basic Modes of Operations ............................................................................................................................ 730 Mixed Modes of Operations ........................................................................................................................... 739 Reference Configurations .............................................................................................................................. 741 UTOPIA Interface Pin Description ................................................................................................................. 742 FIFO Ganging ................................................................................................................................................ 744 Packet Packing .............................................................................................................................................. 744 Default Channel Configuration ....................................................................................................................... 744 UTOPIA Interface Timing ............................................................................................................................... 745 UT Global Registers....................................................................................................................................... 748 UT Per-Interface Registers ............................................................................................................................ 750 UT Register Map ............................................................................................................................................ 764 System Interface................................................................................................................................................... 772 ATM Interfaces............................................................................................................................................... 772 POS Interfaces............................................................................................................................................... 775 Test....................................................................................................................................................................... 778 Scan ............................................................................................................................................................... 778 Boundary Scan .............................................................................................................................................. 778 RAM BIST ...................................................................................................................................................... 778 GFP Payload Area CRC-32 Insertion (Version 2.2 and 2.3 Only) ................................................................. 786 Introduction .................................................................................................................................................... 793 |
同様の部品番号 - TDAT162G52 |
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同様の説明 - TDAT162G52 |
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