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DAC082S085CIMM データシート(PDF) 3 Page - National Semiconductor (TI) |
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DAC082S085CIMM データシート(HTML) 3 Page - National Semiconductor (TI) |
3 / 19 page Pin Descriptions LLP MSOP Pin No. Symbol Type Description 1V A Supply Power supply input. Must be decoupled to GND. 2V OUTA Analog Output Channel A Analog Output Voltage. 3V OUTB Analog Output Channel B Analog Output Voltage. 4 NC Not Connected 5 NC Not Connected 6 GND Ground Ground reference for all on-chip circuitry. 7V REFIN Analog Input Unbuffered reference voltage shared by all channels. Must be decoupled to GND. 8D IN Digital Input Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC. 9 SYNC Digital Input Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. 10 SCLK Digital Input Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin. 11 PAD (LLP only) Ground Exposed die attach pad can be connected to ground or left floating. Soldering the pad to the PCB offers optimal thermal performance and enhances package self-alignment during reflow. www.national.com 3 |
同様の部品番号 - DAC082S085CIMM |
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同様の説明 - DAC082S085CIMM |
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