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74LVXZ161284MEA データシート(PDF) 6 Page - Fairchild Semiconductor |
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74LVXZ161284MEA データシート(HTML) 6 Page - Fairchild Semiconductor |
6 / 11 page www.fairchildsemi.com 6 AC Electrical Characteristics Note 9: Open Drain Note 10: tSKEW is measured for common edge output transitions and compares the measured propagation delay for a given path type: (i) A1–A8 to B1–B8, A9–A13 to Y9–Y13 (ii) B1–B8 to A1–A8 (iii) C14–C17 to A14–A17 Note 11: This parameter is guaranteed but not tested, characterized only. Capacitance Note 12: CI/O is measured at frequency = 1 MHz, per MIL-STD-883B, Method 3012 Symbol Parameter TA = 0°C to +70°CTA = −40°C to +85°C Units Figure Number VCC = 3.0V–3.6V VCC = 3.0V–3.6V VCC—Cable = 3.0V–5.5V VCC—Cable = 3.0V–5.5V Min Max Min Max tPHL A1–A8 to B1–B8 2.0 40.0 2.0 44.0 ns Figure 2 tPLH A1–A8 to B1–B8 2.0 40.0 2.0 44.0 ns Figure 3 tPHL B1–B8 to A1–A8 2.0 40.0 2.0 44.0 ns Figure 4 tPLH B1–B8 to A1–A8 2.0 40.0 2.0 44.0 ns Figure 4 tPHL A9–A13 to Y9–Y13 2.0 40.0 2.0 44.0 ns Figure 2 tPLH A9–A13 to Y9–Y13 2.0 40.0 2.0 44.0 ns Figure 3 tPHL C14–C17 to A14–A17 2.0 40.0 2.0 44.0 ns Figure 4 tPLH C14–C17 to A14–A17 2.0 40.0 2.0 44.0 ns Figure 4 tSKEW LH-LH or HL-HL 10.0 12.0 ns (Note 10) tPHL PLHIN to PLH 2.0 40.0 2.0 44.0 ns Figure 2 tPLH PLHIN to PLH 2.0 40.0 2.0 44.0 ns Figure 3 tPHL HLHIN to HLH 2.0 40.0 2.0 44.0 ns Figure 4 tPLH HLHIN to HLH 2.0 40.0 2.0 44.0 ns Figure 4 tPHZ Output Disable Time 2.0 15.0 2.0 18.0 ns Figure 8 tPLZ DIR to A1–A8 2.0 15.0 2.0 18.0 tPZH Output Enable Time 2.0 50.0 2.0 50.0 ns Figure 9 tPZL DIR to A1–A8 2.0 50.0 2.0 50.0 tPHZ Output Disable Time 2.0 50.0 2.0 50.0 ns Figure 10 tPLZ DIR to B1–B8 2.0 50.0 2.0 50.0 tpEN Output Enable Time 2.0 25.0 2.0 28.0 ns Figure 3 HD to B1–B8, Y9–Y13 2.0 25.0 2.0 28.0 tpDIS Output Disable Time 2.0 25.0 2.0 28.0 ns Figure 3 HD to B1–B8, Y9–Y13 2.0 25.0 2.0 28.0 tpEN–tpDIS Output Enable- 10.0 12.0 ns Output Disable tSLEW Output Slew Rate tPLH B1–B8, Y9–Y13 0.05 0.40 0.05 0.40 V/ns Figure 6 tPHL 0.05 0.40 0.05 0.40 Figure 5 tr, tf tRISE and tFALL 120 120 ns Figure 7 B1–B8 (Note 9), 120 120 (Note 11) Y9–Y13 (Note 9) Symbol Parameter Typ Units Conditions CIN Input Capacitance 3 pF VCC = 0.0V (HD, DIR, A9–A13, C14–C17, PLHIN and HLHIN) CI/O (Note 12) I/O Pin Capacitance 5 pF VCC = 3.3V |
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同様の説明 - 74LVXZ161284MEA |
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