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74AHCT30PW データシート(PDF) 9 Page - NXP Semiconductors |
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74AHCT30PW データシート(HTML) 9 Page - NXP Semiconductors |
9 / 16 page 1999 Nov 30 9 Philips Semiconductors Product specification 8-input NAND gate 74AHC30; 74AHCT30 AC WAVEFORMS handbook, halfpage MNA491 tPHL tPLH VM VM A, B, C, D, E, F, G, H input Y output Fig.5 The input (A, B, C, D, E, F, G and H) to output (Y) propagation delays. FAMILY VI INPUT REQUIREMENTS VM INPUT VM OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC Fig.6 Test circuitry for switching times. TEST S1 tPLH/tPHL open tPLZ/tPZL VCC tPHZ/tPZH GND handbook, full pagewidth open GND VCC VCC VI VO MNA183 D.U.T. CL RT 1000 Ω PULSE GENERATOR S1 Definitions for test circuit: CL = load capacitance including jig and probe capacitance (See Chapter “AC characteristics”); RT = termination resistance should be equal to the output impedance Zo of the pulse generator. |
同様の部品番号 - 74AHCT30PW |
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同様の説明 - 74AHCT30PW |
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