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74ALVCH16500DGG データシート(PDF) 10 Page - NXP Semiconductors

部品番号 74ALVCH16500DGG
部品情報  18-bit universal bus transceiver 3-State
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メーカー  PHILIPS [NXP Semiconductors]
ホームページ  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74ALVCH16500DGG データシート(HTML) 10 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74ALVCH16500
18-bit universal bus transceiver (3-State)
1998 Sep 24
10
AC WAVEFORMS
VCC = 2.3 TO 2.7 V RANGE
1. VM = 0.5 V
2. VX = VOL + 0.15V
3. VY = VOH – 0.15V
4. VI = VCC
5. VOL and VOH are the typical output voltage drop that occur with
the output load.
VCC = 3.0 TO 3.6 V RANGE AND VCC = 2.7 V
1. VM = 1.5 V
2. VX = VOL + 0.3V
3. VY = VOH – 0.3V
4. VI = 2.7 V
5. VOL and VOH are the typical output voltage drop that occur with
the output load.
SW00083
An, Bn
INPUT
VM
tPHL
tPLH
VOL
VI
VM
GND
VOH
Bn, An
OUTPUT
Waveform 1. Input (An, Bn) to output (Bn, An) propagation
times
SW00084
CPXX
INPUT
VM
tPHL
tPLH
VOL
VI
VM
GND
VOH
An, Bn
OUTPUT
tW
LEXX
INPUT
Waveform 2. Latch enable input (LEAB, LEBA) and clock pulse
input (CPAB, CPBA) to output (An, Bn) propagation delays and
latch enable pulse width
tPLZ
tPZL
OEBA
INPUT
VCC
OUTPUT
LOW-to-OFF
OFF-to-LOW
VOL
VOH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
outputs
enabled
outputs
disabled
tPHZ
VM
VM
VM
tPZH
VX
VY
SW00085
OEAB
INPUT
VM
Waveform 3. 3-State enable and disable times
VM
An, Bn
INPUT
VM
tSU
NOTE: The unshaded areas indicate when the input is permitted to change for
predictable output performance.
SW00093
tSU
th
VI
GND
VI
GND
CPXX, LEXX
INPUT
th
Waveform 4. Data set-up and hold times for the An and Bn
inputs to the LEAB, LEBA, CPAB and CPBA inputs


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