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FIN224ACMLX データシート(PDF) 9 Page - Fairchild Semiconductor

部品番号 FIN224ACMLX
部品情報  USerDes 22-Bit Bi-Directional Serializer/Deserializer
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メーカー  FAIRCHILD [Fairchild Semiconductor]
ホームページ  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FIN224ACMLX データシート(HTML) 9 Page - Fairchild Semiconductor

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©2006 Fairchild Semiconductor Corporation
9
www.fairchildsemi.com
FIN224AC Rev. 1.0.7
LVCMOS Data I/O
The LVCMOS input buffers have a nominal threshold
value equal to half VDD. The input buffers are only oper-
ational when the device is operating as a serializer.
When the device is operating as a deserializer, the inputs
are gated off to conserve power.
The LVCMOS 3-STATE output buffers are rated for a
source / sink current of approximately 0.5mA at 1.8V.
The outputs are active when the DIRI signal and either
S1 or S2 is asserted HIGH. When the DIRI signal and
either S1 or S2 is asserted LOW, the bi-directional LVC-
MOS I/Os is in a HIGH-Z state. Under purely capacitive
load conditions, the output swings between GND and
VDDP. When S1 or S2 initially transitions HIGH, the initial
state of the deserializer LVCMOS outputs is zero.
Unused LVCMOS input buffers must be either tied off to
a valid logic LOW or a valid logic HIGH level to prevent
static current draw due to a floating input. Unused LVC-
MOS output should be left floating. Unused bi-directional
pins should be connected to GND through a high-value
resistor. If a FIN224AC device is configured as an unidi-
rectional serializer, unused data I/O can be treated as
unused inputs. If the FIN224AC is hardwired as a deseri-
alizer, unused data I/O can be treated as unused outputs.
The FIN224AC family offers fast and slow LVCMOS
edge rates to meet emissions and loading requirements.
Differential I/O Circuitry
The FIN224AC employs FSC proprietary Current Tran-
sistor Logic (CTL) Input / Output (I/O) technology. CTL is
a low-power, low-EMI differential swing I/O technology.
The CTL output driver generates a constant output
source and sink current. The CTL input receiver senses
the current difference and direction from the correspond-
ing output buffer to which it is connected. This differs
from LVDS, which uses a constant current source output,
but a voltage sense receiver. Like LVDS, an input source
termination resistor is required to properly terminate the
transmission line. The FIN224AC device incorporates an
internal termination resistor on the CKSI receiver and a
gated internal termination resistor on the DS input
receiver. The gated termination resistor ensures proper
termination regardless of direction of data flow. The rela-
tive greater sensitivity of the current sense receiver of
CTL allows it to work at much lower current drive and a
much lower voltage.
During power down mode, the differential inputs are dis-
abled and powered down and the differential outputs are
placed in a HIGH-Z state. CTL inputs have an inherent
failsafe capability that supports floating inputs. When the
CKSI input pair of the serializer is unused, it can reliably
be left floating. Alternately both of the inputs can be con-
nected to ground. CTL inputs should never be connected
to VDD. When the CKSO output of the deserializer is
unused, it should be allowed to float.
Figure 11. Bi-Directional Differential
I/O Circuitry
Phase-Locked Loop (PLL) Circuitry
The CKREF input signal is used to provide a reference to
the PLL. The PLL generates internal timing signals capa-
ble of transferring data at 13 times the incoming CKREF
signal. The output of the PLL is a bit clock that is used to
serialize the data. The bit clock is also sent source syn-
chronously with the serial data stream. There are two
ways to disable the PLL. The PLL can be disabled by
entering the Mode 0 state (S1 = S2 = 0). The PLL dis-
ables immediately upon detecting a LOW on both the S1
and S2 signals. When any of the other modes are
entered by asserting either S1 or S2 HIGH and by pro-
viding a CKREF signal, the PLL powers-up and goes
through a lock sequence. One must wait the specified
number of clock cycles prior to capturing valid data into
the parallel port.
+
+
DS+
DS-
Gated
Termination
(DS Pins Only)
From
Serializer
To
Deserializer
From
Control


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