74V2G132STR datasheet(4/9 Pages) STMICROELECTRONICS

部品番号	74V2G132STR

部品情報	DUAL 2-INPUT SHMITT TRIGGER NAND GATE

Download	9 Pages

Scroll/Zoom	100%

メーカー	STMICROELECTRONICS [STMicroelectronics]

ホームページ	http://www.st.com

Logo

4 / 9 page

74V2G132

4/9

CAPACITANCE CHARACTERISTICS

1) CPD is defined as the value of the IC’s internal equivqlent capacitance which is calculated from the operating current consumption without

load. (Refer to Test Circuit). Average current cqn be obtqined by the following equation. ICC(opr) = CPD x VCC x fIN + ICC

TEST CIRCUIT

CL = 50pF or equivalent (includes jig and probe capacitance)

RL = R1 = 500Ω or equivalent

RT = ZOUT of pulse generator (typically 50Ω)

WAVEFORM: PROPAGATION DELAY (f=1MHz; 50% duty cycle)

Symbol

Parameter

Test Condition

Value

Unit

TA = 25°C

-40 to 85°C

-55 to 125°C

Min.

Typ.

Max.

Min.

Max.

Min.

Max.

CIN

Input Capacitance

4

101010

pF

CPD

Power Dissipation

Capacitance

(note 1)

19

pF

同様の部品番号 - 74V2G132STR

メーカー	部品番号	データシート	部品情報
STMicroelectronics	74V2T132	130Kb / 7P	DUAL 2-INPUT SHMITT TRIGGER NAND GATE
Texas Instruments	SN74LVC2G132	1Mb / 20P	[Old version datasheet] Dual 2-Input NAND Gate With Schmitt-Trigger Inputs
Unisonic Technologies	U74LVC2G132	181Kb / 5P	DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
Texas Instruments	SN74LVC2G132	946Kb / 18P	[Old version datasheet] Dual 2-Input NAND Gate With Schmitt-Trigger Inputs
	SN74LVC2G132	241Kb / 13P	[Old version datasheet] DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
	SN74LVC2G132	426Kb / 14P	[Old version datasheet] DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS
National Semiconductor ...	DM74S132	56Kb / 3P	Quad 2-Input Schmitt Trigger NAND Gate
Motorola, Inc	SN54LS132	158Kb / 5P	QUAD 2-INPUT SCHMITT TRIGGER NAND GATE
Toshiba Semiconductor	TC7WH00FU	195Kb / 6P	DUAL 2-INPUT NAND GATE
Panasonic Semiconductor	74LVC2G00	91Kb / 16P	Dual 2-input NAND gate