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74LVC16374ADL データシート(PDF) 2 Page - NXP Semiconductors |
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74LVC16374ADL データシート(HTML) 2 Page - NXP Semiconductors |
2 / 10 page Philips Semiconductors Product specification 74LVC16374A/ 74LVCH16374A 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State) 2 1998 Mar 17 853-2028 19111 FEATURES • 5 volt tolerant inputs/outputs for interfacing with 5V logic • Wide supply voltage range of 1.2 V to 3.6 V • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple power and ground pins for minimum noise and ground bounce • Direct interface with TTL levels • All data inputs have bus hold (74LVCH16374A only) • High impedance when V CC = 0 DESCRIPTION The 74LVC(H)16374A is a 16-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-State outputs for bus oriented applications. The 74LVC16374A consists of 2 sections of eight positive edge-triggered flip-flops. A clock (CP) input and an output enable (OE) are provided for each octal. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. These features allow the use of these devices in a mixed 3.3V/5V environment. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The 74LVCH16374A bus hold data inputs eliminates the need for external pull up resistors to hold unused inputs. PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1OE 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q5 GND 1Q6 1Q7 2Q0 2Q1 GND 1Q4 2Q2 2Q3 VCC 2Q4 2Q5 2D5 2D4 VCC 2D3 2D2 GND 2D1 2D0 1D7 1D6 GND 1D5 1D4 VCC 1D3 1D2 GND 1D1 1D0 1CP 21 22 23 24 25 26 27 28 GND 2Q6 2Q7 2OE 2CP 2D7 2D6 GND SW00074 QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay Cp to Qn CL = 50pF VCC = 3.3V 3.8 ns fMAX Maximum clock frequency 150 MHz CI Input capacitance 5.0 pF CPD Power dissipation capacitance per flip-flop VCC = 3.3V1 30 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 48-Pin Plastic SSOP Type III –40 °C to +85°C 74LVC16374A DL VC16374A DL SOT370-1 48-Pin Plastic TSSOP Type II –40 °C to +85°C 74LVC16374A DGG VC16374A DGG SOT362-1 48-Pin Plastic SSOP Type III –40 °C to +85°C 74LVCH16374A DL VCH16374A DL SOT370-1 48-Pin Plastic TSSOP Type II –40 °C to +85°C 74LVCH16374A DGG VCH16374A DGG SOT362-1 |
同様の部品番号 - 74LVC16374ADL |
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同様の説明 - 74LVC16374ADL |
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