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DS3903 データシート(PDF) 9 Page - Maxim Integrated Products |
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DS3903 データシート(HTML) 9 Page - Maxim Integrated Products |
9 / 11 page Triple 128-Position Nonvolatile Digital Potentiometer _____________________________________________________________________ 9 write process tw to the EEPROM memory. All inputs are disabled during this write cycle. The DS3903 is capable of an 8-byte page write. A page write is initiated the same way as a byte write, but the master does not send a stop condition after the first data byte. Instead, after the slave acknowledges the data byte has been received, the master can send up to seven more data bytes using the same nine-clock sequence. After a write to the last byte in the page, the address returns to the beginning of the same page. The master must then terminate the write cycle with a stop condition or the data clocked into the DS3903 is not latched into EEPROM. Note that in order for eight bytes to be stored sequentially (and to prevent looping around), the address byte must be set to the beginning of the desired page (three LSBs of the address are 0). For detailed information concerning page operations, see the Potentiometer Memory Organization section. Acknowledge Polling Once the internally timed write has started and the DS3903 inputs are disabled, acknowledge polling can be initiated. The process involves transmitting a start condition followed by the device address. The R/W bit signifies the type of operation that is desired. The read or write sequence is only allowed to proceed if the internal write cycle has completed and the DS3903 responds with a zero. Read Operations After receiving a matching address byte with the R/W bit set high, the device goes into the read mode of opera- tion. There are three read operations: current address read, random read, and sequential address read. Current Address Read The DS3903 has an internal address register that main- tains the address used during the last read or write operation, incremented by one. This data is maintained as long as VCC is valid. If the most recent address was the last byte in memory, then the register resets to the first address. This address stays valid between opera- tions as long as power is available. Once the device address is clocked in and acknowl- edged by the DS3903 with the R/W bit set to high, the current address data word is clocked out. The master does not respond with a zero, but does generate a stop condition afterwards. Random Address Read A random read requires a dummy byte write sequence to load in the data word address. Once the device address and data address bytes are clocked in by the master, and acknowledged by the DS3903, the master must generate another start condition. The master now initiates a current address read by sending the device address with the R/W bit set high. The DS3903 acknowledges the device address and serially clocks out the data byte. Sequential Address Read Sequential reads are initiated by either a current address read or a random address read. After the mas- ter receives the first data byte, the master responds with an acknowledge. As long as the DS3903 receives this acknowledge after a byte is read, the master can clock out additional data words from the DS3903. After reaching address FFh, it resets to address 00h. The sequential read operation is terminated when the master initiates a stop condition. The master does not respond with a zero. For a more detailed description of 2-wire theory of operation, see the following section. 2-Wire Serial Port Operation The 2-wire serial port interface supports a bidirectional data transmission protocol with device addressing. A device that sends data on the bus is defined as a trans- mitter, and a device receiving data as a receiver. The device that controls the message is called a “master.” The devices that are controlled by the master are “slaves.” The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the start and stop con- ditions. The DS3903 operates as a slave on the 2-wire bus. Connections to the bus are made through the open-drain I/O lines, SDA and SCL. The following I/O terminals control the 2-wire serial port: SDA, SCL, and A0. Timing diagrams for the 2-wire serial port can be found in Figures 2 and 3. Timing information for the 2- wire serial port is provided in the AC Electrical Characteristics table for 2-wire serial communications. |
同様の部品番号 - DS3903 |
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同様の説明 - DS3903 |
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