5-1

FACT DATA

12Stage Binary Ripple Counter

The MC74AC4040 consists of 12 master-slave flip-flops. The output of each

flip-flop feeds the next and the frequency at each output is half that of the preceding

one. The state of the counter advances on the negative-going edge of the Clock

input. Reset is asynchronous and active-high.

State changes of the Q outputs do not occur simultaneously because of internal

ripple delays. Therefore, decoded output signals are subject to decoding spikes

and may have to be gated with the Clock of the MC74AC4040 for some designs.

• 140 MHz Typ. Clock

• Outputs Source/Sink 24 mA

• Operating Voltage Range: 2.0 to 6.0 V

• High Noise Immunity

15

16

14

13

12

11

10

2

1

3

4

5

6

7

VCC

9

8

Q11

Q10

Q8

Q9

RESET CLK

Q1

Q12

Q6

Q5

Q7

Q4

Q3

Q2

GND

FUNCTION TABLE

Clock

Reset

Output State

L

No Change

L

Advance to next state

X

H

All Outputs are low

MC74AC4040

12-STAGE

BINARY RIPPLE

COUNTER

N SUFFIX

CASE 648-08

PLASTIC

D SUFFIX

CASE 751B-05

PLASTIC

LOGIC DIAGRAM

CLOCK

10

11

RESET

PIN 16 = VCC

PIN 8 = GND

9

7

6

5

3

2

4

13

12

14

15

1

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q11

Q12