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ADM1177 データシート(PDF) 9 Page - Analog Devices

部品番号 ADM1177
部品情報  Hot Swap Controller and Digital Power Monitor with Soft-Start Pin
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

ADM1177 データシート(HTML) 9 Page - Analog Devices

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Preliminary Technical Data
ADM1177
Rev. PrD | Page 9 of 16
point (4). The initial cycle delay (time point 2 to time point 4) is
related to CTIMER by equation:
tINITIAL ~= 270 × CTIMER ms/μF
(7)
When the initial timing cycle terminates, the device is ready to
start a hotswap operation (assuming ON pin is asserted). In the
example shown in Figure 4, the ON pin was asserted at the
same time as VCC was applied, so the hotswap operation starts
immediately after time-point (4). At this point the FET gate is
charged up with a 12 μA current source. At timepoint (5) the
threshold voltage of the FET is reached and the load current
begins to flow. The FET is controlled to keep the sense voltage
at 100 mV (this corresponds to a maximum load current level
defined by the value of RSENSE). At timepoint (6) VGATE and VOUT
have reached their full potential and the load current has settled
to its nominal level. Figure 5 illustrates the situation where the
ON pin is asserted after VVCC is applied.
VVCC
VON
VGATE
VOUT
VTIMER
INITIAL TIMING
CYCLE
(1)
(2)
(3) (4) (5)
(6)
VSENSE
Figure 4. Start-up (ON asserts as power is applied)
VVCC
VON
VGATE
VOUT
VTIMER
INITIAL TIMING
CYCLE
(1)
(2)
(3)(4)
(5)(6)
VSENSE
(7)
Figure 5. Start-up (ON asserts after power is applied)
HOTSWAP RETRY CYCLE ON ADM1177-1
With the ADM1177-1 the device will turn off the FET after an
overcurrent fault, and will then use the TIMER pin to time a
delay before automatically retrying to hotswap.
As with all ADM1177 devices, on overcurrent fault is timed by
charging the TIMER cap with a 60 μA pull-up current, and
when the TIMER pin reaches 1.3 V the fault current limit time
has been reached and the GATE pin is pulled down. On the
ADM1177-1, the TIMER pin is then pulled down with a 2 μA
current sink. When the TIMER pin reaches 0.2 V, it will
automatically restart the hotswap operation.
The cool down period is related to CTIMER by equation:
tCOOL ~ = 550 × CTIMER ms/μF
(8)
The retry duty cycle is thus given by
tFAULT/(tCOOL + tFAULT ) × 100% = 3.8%
(9)


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