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ADF7021 データシート(PDF) 6 Page - Analog Devices |
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ADF7021 データシート(HTML) 6 Page - Analog Devices |
6 / 44 page ADF7021 Preliminary Technical Data Rev. PrI | Page 6 of 44 Parameter Min Typ Max Unit Test Conditions LOGIC INPUTS Input High Voltage, VINH 0.7 × V DD V Input Low Voltage, VINL 0.2 × VDD V Input Current, IINH/IINL ±1 μA Input Capacitance, CIN 10 pF Control Clock Input 50 MHz LOGIC OUTPUTS Output High Voltage, VOH DVDD − 0.4 V IOH = 500 μA Output Low Voltage, VOL 0.4 V IOL = 500 μA CLKOUT Rise/Fall 5 ns CLKOUT Load 10 pF TEMPERATURE RANGE (TA) −40 +85 °C POWER SUPPLIES Voltage Supply VDD 2.3 3.6 V All VDD pins must be tied together Transmit Current Consumption VDD = 3.0 V, PA is matched into 50 Ω 0 dBm 12.7 mA FRF = 460 MHz 10 dBm 21 mA FRF = 460 MHz 0 dBm 19.3 mA FRF = 868 MHz 10 dBm 28 mA FRF = 868 MHz Receive Current Consumption Low Current Mode 20 mA High Sensitivity Mode 22 mA Power-Down Mode Low Power Sleep Mode 0.1 1 μA 1 For definition of frequency deviation, see the Register 2—Transmit Modulation Register section. 2 Measured as maximum unmodulated power. Output power varies with both supply and temperature. 3 For matching details, see the LNA/PA Matching section. 4 Sensitivity for combined matching network case is typically 2 dB less than separate matching networks. 5 See Table 8 for a description of different receiver modes. 6 Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications. |
同様の部品番号 - ADF7021 |
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同様の説明 - ADF7021 |
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